Simulation of a high performance MOSFET with a quantum wirestructure incorporating a periodically bent Si-SiO2 interface

A MOSFET using a serrated quantum wire structure that produces one-dimensional electron confinement shows excellent subthreshold characteristics and enhanced drive capability compared to a conventional MOSFET with a flat Si-SiO₂ interface. We studied the quantum wire structure with its periodically bent Si-SiO₂ interface using simulations. The potential in the convex regions of the silicon is 0.34 V higher than that in the concave ones when the bending angle is 90°, the bending period is 100 nm, substrate doping is 3.0×10 ¹⁷ cm^-3, and a gate voltage is 0.1 V. Because of this increase in potential in the convex regions, electrons are confined in a narrow width of 13 nm in the convex regions. This 1-D electron confinement effect by the bent Si-SiO₂ interface is clearly observed at low gate voltage and is reduced as the gate voltage becomes higher. Due to the confinement effect, drain current in the MOSFET with this quantum wire structure is 270 times higher than that of a MOSFET with a flat Si-SiO₂ interface at a gate voltage of 0.05 V. In addition, the short-channel effect is more effectively suppressed in this MOSFET than in a conventional MOSFET     

Measurements of leakage currents and the capacitance of the storagecapacitor in a single DRAM cell

Methods of measuring leakage currents and the capacitance of the storage capacitor in a single DRAM cell have been developed for correlation with the electrode shape of the capacitor. In the circuit used for these measurements, the plate electrode of the storage capacitor is connected to the gate of the MOSFET which amplifies the voltage variations of the storage capacitor during the measurements. Here, only a conventional transistor parameter analyzer and a capacitance meter are required for the measurements. For the capacitance measurement, the linear region characteristics of the MOSFET are used to simplify the analysis. For the leakage current measurement, however, the subthreshold region characteristics of the MOSFET are used to enhance the accuracy of the measurement. The results show that the very low leakage currents (down to below 0.1 fA) and the capacitance (37.5 fF) of the storage capacitor can be measured accurately. Further, the leakage current-voltage characteristics of the storage capacitor are discussed by comparing with those of a large area planar capacitor whose structure is the same as the storage capacitor     

A simple switched-capacitor-based capacitance-to-frequency converter

A simple integrated capacitance-to-frequency converter is presented. Its core is a switched-capacitor integrator. Under the control of a switch clock the converter produces a square-wave signal whose frequency depends on an external capacitor. It is insensitive to parasitic capacitance and not affected by the op amp offset voltage. Moreover, this converter has a linear capacitance-to-frequency transform characteristic. This experimental circuit has been implemented by a low voltage double-polysilicon 5-m NMOS technology. Since the circuit is cost-effective and power consumption is low (less than 10 mW), such a converter is suitable for many mesurement systems which use a capacitor as a sensor. For example, it can be used for atmospheric pressure measurement in a meteorological balloon which cannot be reclaimed after release.     

The temperature dependence of threshold voltages in submicrometer CMOS

The temperature coefficient of the threshold voltage in long buried-p-channel MOSFET isdV_{th}/dT = 2.02mV/°C, which is much larger than that in the long enhancement-mode n-channel MOSFET (-1.27 mV/°C). The difference is caused by the charge freeze-out phenomenon in the buried-channel MOSFET. The absolute value of the temperature coefficient of the threshold voltage|dV_{th}/dT|, decreases with decreasing channel length in the n-channel MOSFET, however, it increases with decreasing channel length in the submicrometer p-channel MOSFET. The difference results from the majority-carrier spill-over phenomenon in the buried-p-channel MOSFET.     

Erase/write cycle tests of n-MOSFETs with Si-implantedgate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V     

An experimental study of the BO-MOS dynamic RAM cell

A novel structure of a one-transistor dynamic MOS RAM cell is developed for higher integration. The buried-oxide MOS (BO-MOS) RAM cell consists of a planar MOSFET transfer gate and a storage capacitor of buried N⁺diffusion. This three-dimensional structure results in a cell size of6F^{2}with a minimum feature sizeFand the large capacitance ratio of storage to bit-line which is about 4 times that of a typical commercial 64-kbit RAM cell. The soft-error-immunity cell structure is also taken into account. Static device characteristics of the planar MOSFET transfer gate built on an epitaxial layer and the buried storage capacitance are investigated relating to doses of boron implantation to the channel and substrate. Dynamic WRITE/READ operations are performed with an experimental 4 × 10 cell array implemented withF = 4-µm features. The technology offers the possibilities of a high density dynamic MOS RAM with a single poly-Si process.     

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structuresfor high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V_th lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V_th lowering at 0.4-μm gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4-μm gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4-μm gate length     

A Sub-1-V, 10 ppm/ °C, Nanopower Voltage Reference Generator

An extreme low power voltage reference generator operating with a supply voltage ranging from 0.9 to 4 V has been implemented in AMS 0.35-mum CMOS process. The maximum supply current measured at the maximum supply voltage and at 80degC is 70 nA. A temperature coefficient of 10 ppm/degC is achieved as the combined effect of 1) a perfect suppression of the temperature dependence of mobility; 2) the compensation of the channel length modulation effect on the temperature coefficient; and 3) the absence of the body effect. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -53 and -42 dB, respectively. The occupied chip area is 0.045 mm².     

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET'sand its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi₂ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8×10⁶ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V     

Positive flatband voltage shift in MOS capacitors on n-type GaN

GaN MOS capacitors were fabricated using silicon dioxide deposited by low-pressure chemical vapor deposition oxide at 900°C. The MOS capacitor flatband voltage shift versus temperature was used to determine a pyroelectric charge coefficient of 3.7 × 10⁹ q/cm²-K, corresponding to a pyroelectric voltage coefficient of 7.0 × 10⁴ V/m-K     

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO2

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm²/V.s and drain breakdown voltage exceeding 15 V.     

Elimination of bipolar induced drain breakdown and singletransistor latch in submicron PD SOI MOSFET

For the first time, we report the combined application of a SiGe source and a delta-doped p⁺ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications     

高速高精度SAR ADC电容电压系数校正

基于XFAB工艺参数,设计了一种不受电容电压系数影响的高速高精度SAR ADC。在理论上定性分析了电容电压系数对高速高精度SAR ADC的影响,并使用Matlab进行定量分析。分析结果表明,1阶与2阶电容电压系数对ADC性能的影响具有不同的特点。针对1阶电容电压系数,使用改进的分裂电容结构进行消除;针对2阶电容电压系数,使用分段数字补偿来进行校正。校正完成以后,电容电压系数引起的非线性误差可以从±11.7 LSB降到±0.5 LSB以下,无杂散动态范围可以提高10 dB以上。     

A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator

A majority-carrier distribution model and a channel potential-profile model, in which the barrier-lowering effect is taken into account, are proposed for a buried-channel MOSFET (BC-MOSFET/ SOI). Simple expressions for threshold voltage and drain breakdown voltage were derived from the models for a short-channel BC-MOSFET/ SOI. The comparison between theory and experimental results shows reasonable agreement. The drain-bias coefficient γ of threshold voltage for BC-MOSFET's/ SOI is approximately proportional to TND^-1Leff^-2, where T, ND, and Leffare the temperature, the doping concentration in the channel region, and the channel length, respectively. The coefficient γ depends slightly on the drain bias. BC-MOSFET's/SOI are able to be more miniaturized than surface-channel MOSFET's (SC-MOSFET's) at the small power source voltage, and SC-MOSFET's are able to be more miniaturized than BC-MOSFET's/SOI at the large drain bias. It is shown that the conventional, simple scaling scheme, which holds the constant electric field, is not applicable to BC-MOSFET's/SOI. The power source voltage has to be fixed when dimensions and doping concentrations are scaled down. On the other hand, only the channel region thickness has to be fixed when the power source voltage is scaled down.     

Low programming voltage floating gate analogue memory cells in standard VLSI CMOS technology

Floating gate MOSFET structures were fabricated in a standard 2 mu m double-polysilicon CMOS process which requires programming voltages of only 6.5-9 V. This considerable reduction in programming voltage is achieved by simultaneously exploiting tunnelling through the interpolysilicon oxide and capacitive geometries whose top poly-layers overlap the edges of the lower poly-layers.<>     

The COMFET—A new high conductance MOS-gated device

A new MOS gate-controlled power switch with a very low on-resistance is described. The fabrication process is similar to that of an n-channel power MOSFET but employs an n^--epitaxial layer grown on a p⁺substrate. In operation, the epitaxial region is conductivity modulated (by excess holes and electrons) thereby eliminating a major component of the on-resistance. For example, on-resistance values have been reduced by a factor of about 10 compared with those of conventional n-channel power MOSFET's of comparable size and voltage capability.     

A GaAs MOSFET with a liquid phase oxidized gate

Low leakage current density (as low as 10^-8 A/cm² at an applied voltage of 5 V) and high breakdown electrical field (larger than 4.5 MV/cm) of the liquid phase chemical-enhanced oxidized GaAs insulating layer enable application to the GaAs MOSFET. The oxide layer is found to be a composite of Ga₂O₃, As, and As₂O₃. The n-channel depletion mode GaAs MOSFET's are demonstrated and the I-V curves with complete pinch-off and saturation characteristics can be seen. A transconductance larger than 30 mS/mm can be achieved which is even better than that of MESFET's fabricated on the same wafer structure     

Low-voltage coefficient capacitors for VLSI processes

The addition of a high-quality capacitor structure to a 1-μm digital CMOS process is considered to allow the fabrication of mixed analog and digital VLSI circuits. Two approaches have been examined which require minimal changes in the existing process. The first involves a high-dose arsenic implant through the thin (225 A) gate oxide to produce n⁺ single-crystal silicon bottom plates. This approach produced a capacity of 154 nF/cm² with a maximum voltage coefficient of 210 p.p.m./V over a bias range of ±7.5 V. In the second approach the high-dose implant is performed prior to the gate oxidation. Impurity-concentration-enhanced oxidation of the n⁺ silicon bottom plates can then be exploited during the subsequent gate oxidation to grow simultaneously a capacitor dielectric of varying thickness. Capacities of 40-90 nF/cm² have been produced with voltage coefficients ranging from 35 to 125 p.p.m./V, respectively     

High-performance pulse-width modulation AC/DC controller using novel under voltage lockout circuit according to Energy Star VI standard

This paper proposes a high-performance pulse-width modulation (PWM) AC/DC controller, which can drive a high-voltage (HV) 650-V power metal-oxide-semiconductor field-effect Transistor (MOSFET) in typical applications of adapters in portable electronic devices. In order to reduce the standby power consumption and improve the response speed in the start-up state, an improved under voltage lockout (UVLO) circuit without a voltage reference source or comparator is adopted. The AC/DC controller is fabricated using a 40-V 0.8-μm one-poly two-metal (1P2M) CMOS process, and it only occupies 1410 × 730 μm². A 12 V/2 A flyback topology for quick-charge application is illustrated as the test circuit, which is currently one of the most advanced power adapters in use. Test values show that the turn-on and the turn-off threshold voltages are 19.318 and 8.01 V, respectively. A high hysteresis voltage of 11.308 V causes the value of the power-charging capacitor to decrease to as low as 1 μF to reduce production cost. In addition, the start-up current of 2.3 μA is extremely small, and is attributed to a reduction in the system's standby power consumption. The final test results of the overall system are proven to meet the Energy Star VI standard. The controller has already been mass produced for industrial applications.     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.