Second generation I/SUP 2/L/MTL: a 20 ns process/structure

A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following characteristics at 100 /spl mu/A injector current: /spl beta//SUB U//SUP eff//spl ges/4 for all collectors at 25/spl deg/C and /spl ges/2.5 at -55/spl deg/C, /spl alpha//SUB rec///spl alpha//SUB F//spl cong/0.58 and /spl tau/~/SUB d/=18-20 ns from -55 to 125/spl deg/C, and a speed-power product of 1.4 pJ at 25/spl deg/C. At low injector currents, a constant speed-power product of 0.36 pJ at 25/spl deg/ was obtained.     

Schottky I/SUP 2/L

Schottky I/SUP 2/L uses the principles of integrated injection logic (I/SUP 2/L/MTL) and the properties of ion implantation to obtain improved performance at the same densities as conventional I/SUP 2/L. Schottky diodes are formed in the multicollectors of the switching transistor and reduce the signal swing, thus improving the power delay efficiency. An increase in the intrinsic speed limit is also feasible. The Schottky I/SUP 2/L structure and characteristics are described and contrasted with conventional I/SUP 2/L. A model which is useful for its design is discussed. Integrated test structures which provide direct comparison between conventional and Schottky I/SUP 2/L performance have been fabricated. The experimental results demonstrate a factor of 2 improvement in power-delay efficiency of Schottky I/SUP 2/L over conventional I/SUP 2/L.     

An investigation of the intrinsic delay (speed limit) in MTL/I/SUP 2/L

Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. The injection model is used, into which new charge storage parameters are introduced. The majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. A device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.     

A 25 ns 8K /spl times/ 8 static MTL/I/SUP 2/L RAM

An experimental 8K /spl times/ 8-bit static MTL RAM has been successfully fabricated in a standard bipolar manufacturing process with 2-/spl mu/m epitaxy and junction isolation, using design rules of 2.2 /spl mu/m minimum dimensions. Despite conservative processing and less aggressive photolithography compared to the most advanced static FET RAMs, a significantly better performance of 25-ns access has been achieved at a comparable bit density of 1730 bits/mm/SUP 2/. Another outstanding feature is the very low power dissipation of only 8 mW in standby and 270 mW at 50-ns or 150 mW at 100 ns-cycle operation. A holding power below 1/spl mu/W has been measured to retain the information in the complete cell array. A further significant advantage is the insensitivity to /spl alpha/-particle radiation which is a characteristic of the MTL structure.     

Schottky collector I/SUP 2/L

A new I/SUP 2/L gate which promises increased packing density and increased speed is discussed. It incorporates the use of a Schottky contact as the collector of the vertical switching transistor of an I/SUP 2/L gate. Calculations and experiments show that the problems associated with this structure (low downward beta) can be controlled by limiting both the fan-out and the fan-in. Delays of less than 10 ns have been measured using a 10-/spl mu/m technology and a 6-/spl mu/m-thick epi. A divide-by-two circuit with a maximum toggle frequency of 12.5 MHz has been built. The additional fan-in limitation of the logic is described.     

Stacked I/SUP 2/L structures

In LSI environments where the available power supply is greater than 800 mV, integrated injection-logic's (I/SUP 2/L's) inherent high level of power efficiency is restored by stacking. The use of stacked I/SUP 2/L structures in the realization of random logic and regular arrays is studied. Two approaches are considered and compared. Design examples are given including adders, a seven segment display decoder, and a control logic function. The degradation of the speed of operation because of the stacking is analyzed and experimentally verified.     

Scaling I/SUP 2/L for VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I/SUP 2/L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I/SUP 2/L devices with geometries >1 /spl mu/m is described and examples of scaled devices fabricated with e-beam slice writing techniques are given. It is shown that the I/SUP 2/L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submicron geometries are summarized and the performance attainable with a submicron device design is predicted.     

Considerations for high-speed and analog-circuit-compatible I/SUP 2/L and the analysis of Poly I/SUP 2/L

Expressions are derived for minimum propagation-delay time and DC operational conditions in the I/SUP 2/L circuit configuration, and are applied to several kinds of I/SUP 2/L limitations. 1) Ultimately achievable (roughly 0.34 ns, fan-out of 2) and reasonably expected minimum propagation-delay values (0.75-1.0 ns considering simple n-p-n limitations) are estimated. 2) Speed improvements of the standard I/SUP 2/L structure via doping level adjustment is shown to be minimal (it is primarily useful for ensurance of DC operation). 3) Requiring analog compatibility further constrains performance; a figure of merit of about 1 to 2 V/ns is derived and experimentally confirmed for the product of analog device BV/SUB CBO/ and I/SUP 2/L speed for standard epitaxial I/SUP 2/L processing. Radical techniques using dual buried layers, dual epitaxial layers, or Poly I/SUP 2/L offer considerably enhanced performance by attacking the parameter with primary leverage on these tradeoffs: base-to-buried layer spacing W/SUB epi/. Analysis of Poly I/SUP 2/L reveals specific advantages.     

Schottky I/SUP 2/L (substrate fed logic)-an optimum form of I/SUP 2/L

A modified form of Schottky I/SUP 2/L (originally called substrate fed logic) has been developed, differing from the earlier process mainly in the extrinsic n-p-n base profile. Heavier boron doping in this region has led to reduced charge storage so that minimum delays as low as 8 ns/gate at a power of 50 /spl mu/W are now achieved in ring oscillator circuits. The reduced minimum delay also applies to more complex gates, as demonstrated by a D-type flip-flop which operated at 20 MHz with a power dissipation of 70 /spl mu/W/gate. The excellent yield and high packing density which have been obtained on trial circuits demonstrate that the process is capable of very large scale integration.     

I/SUP 2/L DC functional requirements

Factors controlling the DC operational limits of integrated injection logic (I/SUP 2/L) imposed by the interaction between the inverse n-p-n switching transistors and the lateral p-n-p transistor formed with the injector are discussed. The operational limit is shown to be a function only of structural and doping level parameters. An upper limit on epitaxial resistivity is shown to result.     

I/SUP 2/L current gain design

A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell.     

Base current of I/SUP 2/L transistors

For the I/SUP 2/L n-p-n transistor, a method is presented which allows the base current to be split into various components. This has been achieved by comparing, at a fixed emitter-base voltage, the base current of I/SUP 2/L devices, different in geometry. Several precautions against parasitic effects are described. The measurements have been carried out in the emitter-base voltage range of 540-650 mV. Mathematical expressions are derived for the measured current densities and are compared with theory. It is demonstrated that bandgap narrowing effects in the heavily doped regions of the device have to be taken into account in order to explain the difference between experimental values and theory. Furthermore, it is shown that the experimentally determined base current of a four-collector I/SUP 2/L gate is in good agreement with the calculations.     

A single-chip I/SUP 2/L PCM codec

A single chip CPCM codec is described. This chip, which is fabricated in bipolar technology, meets all the D3 specifications. The circuit is capable of operating in a fully asynchronous transmit and receive mode, and provisions are made for zero code suppression and A/B signaling. Even with this signaling, the codec achieves a worst case idle channel noise of 13 dBrnC0.     

I/SUP 2/L with polysilicon diode contact

A polysilicon diode is used instead of a Schottky diode in I/SUP 2/L/MTL to reduce the signal swing. The new method enables improvement of the power-delay product of a conventional I/SUP 2/L, which has heavily doped collectors, without detriment to process simplicity, while retaining high-packing density and compatibility with other bipolar circuits. Experiments demonstrate a factor of 2.5 to 3 improvement in propagation delay at a low-current level. However, high-current operation is restricted by decreased noise margin with increasing current level.     

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

A self-aligned I/sup 2/L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aIigned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-/spl mu/m design roles and fabricated with this technology exhibit gate delays as small as 0.8 ns at lC = 100 -/spl mu/A for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.     

A one-chip I/SUP 2/L controller for appliances

An I/SUP 2/L LSI chip is described that can control the machine functions of home appliances. Using linear-compatible I/SUP 2/L, no additional peripheral ICs, such as drivers for triacs and displays, are needed. The program sequence is stored in a mask-programmable read-only memory. In this way, program changes are easy. For the ROM matrix and the A/D converter, new configurations have been developed.     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

A new high-voltage analog-compatible I/SUP 2/L process

A new technique for realizing high-performance I/SUP 2/L circuits simultaneously with high-voltage analog circuits is described. The method is flexible and may be used with any standard linear bipolar process. Only one additional noncritical masking step and one phosphorus implant are required to form the I/SUP 2/L n-wells. Experimental results are presented which show I/SUP 2/L betas of greater than eight per collector with the I/SUP 2/L BV/SUB CEO/ exceeding 3 V. The measured minimum average propagation delay is 40 ns using a 14 /spl mu/m thick, 5 /spl Omega/.cm epitaxial layer, while the analog BV/SUB CEO/ exceeds 50 V.     

A new high speed I/SUP 2/L structure

A new improved I/SUP 2/L structure is discussed which has been shown to operate at high speeds with large fan-out capabilities while retaining low power operation. The new `up-diffused' structure is fabricated in such a fashion that Schottky diodes can be readily incorporated. With the addition of Schottky clamps between the collector and base of the n-p-n switching transistor, gate delays as low as 2.5 ns have been achieved.     

Modeling the dynamic behavior of I/SUP 2/L

The validity of the charge control approach is checked for the normal (upward) operation of an I/SUP 2/L gate, leading to the conclusion that deviations are mainly due to the distributed nature of the base resistance. An alternative method is presented to determine the relevant device parameters, starting from experimental data. An equivalent model, incorporating the distributed base resistance, is proposed and verified by simulating the power delay characteristics of ring oscillators.