块浮点FFT处理器的有限字长效应分析

研究了基于基8算法的块浮点FFT处理器的有限字长效应问题,提出了一种基于理论统计分析的静态模型。在不考虑输入信号的量化误差和系数量化误差情况下,对基8单元和加权过程的误差进行了分析;给出了有限字长效应所造成的误差随着频率点数和级数的变化趋势。通过SPEED开发平台得到的硬件仿真结果验证了该方法估计字长效应的正确性,可以将其应用于工程分析。     

Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic

In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.     

Development of a Reconfigurable Platform for Manufacturing Equipment Control

In modern manufacturing equipment control area, controller is required to deliver higher computing capability for adopting advanced algorithms to meet speed and accuracy requirements, and reconfigurabilities for changing or (and) adding features or functions. This paper presents a methodology in design and implementation of a high performance and reconfigurable platform for manufacturing equipment control. This methodology is in virtue of system on a programmable chip (SoPC) technology but replacing the on-chip processor by an external high performance, floating-point digital signal processor (DSP). The application of the DSP is designed as a multi-threaded framework, which has more flexibilities than a traditional single-loop one. Furthermore, the field programmable gate array (FPGA) system can be reconfigured easily and quickly to meet a new requirement by dragging and dropping pre-built components in a SoPC building environment. As a result, the controller platform is more reconfigurable in terms of algorithms and functions. This platform is implemented in a 3-axis milling machine control and the result indicates that the design and implementation presented in this paper is feasible.     

一种FFT并行处理机的设计与实现

专用指令集处理器具有数字信号处理器的可编程性和专用处理电路的高速性,以专用指令集处理器为核心构成的阵列式并行处理系统在高速实时处理方面有着非常重要的应用．为此,提出了一种基于专用指令集处理器的快速傅里叶变换并行处理机实现方法．设计了基于精简指令集处理器体系结构的可编程处理单元,以其为核心构成并行处理系统,采用通信矩阵解决了并行系统内各个处理单元间的数据交换问题,实现了1024点快速傅里叶变换的并行处理．实验结果表明,在快速傅里叶变换处理方面,其处理速度比典型数字信号处理器提高30％,且具有系统并行规模大、功能灵活可变、设计复杂程度适当、设计重复利用性好的优点,非常适合在现场可编程逻辑门阵列中以SoC的形式实现．     

ASIC Design and Implementation for Digital Pulse Compression Chip

A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, i.e. let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space (TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91.6μs. The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.     

Development of a Reconfigurable Platform for Manufacturing Equipment Control

In modern manufacturing equipment control area,controller is required to deliver higher computing capability for adopting advanced algorithms to meet speed and accuracy requirements,and reconfigurabilities for changing or(and)adding features or functions.This paper presents a methodology in design and implementation of a high performance and reconfigurable platform for manufacturing equipment control.This methodology is in virtue of system on a programmable chip(SoPC)technolo- gy but replacing the on-chip processor by an external high performance,floating-point digital signal processor(DSP).The appli- cation of the DSP is designed as a multi-threaded framework,which has more flexibilities than a traditional single-loop one.Fur- thermore,the field programmable gate array(FPGA)system can be reconfigured easily and quickly to meet a new requirement by dragging and dropping pre-built components in a SoPC building environment.As a result,the controller platform is more recon- figurable in terms of algorithms and functions.This platform is implemented in a 3-axis milling machine control and the result indicates that the design and implementation presented in this paper is feasible.     

基于SOPC的可重构运动控制平台（英文）

用于现代运动控制领域的控制器,既需具备强大的计算能力来满足速度和精度的要求,还需具备可重构性能,以便更改或添加新功能。本文提出一种可重构运动控制平台的设计方法,本设计利用可编程片上系统（SOPC）技术,为提高计算能力,用浮点数字信号处理器（DSP）代替片上定点处理器。软件采用基于多线程的框架,比单线程的架构更具柔性。在SOPC Builder工具下对功能模块进行重新组合,可对现场可编程门阵列（FPGA）系统进行快速配置以适应新的功能需求。从算法和功能上来说,该平台具有较好的可重构性,通过对三轴铣床的控制,证明了该设计方法的可行性。     

一种基于FPGA的高精度浮点运算处理器系统

本文叙述了基于SDartan3型FPGA的流水线浮点处理器的设计。它是运用在设计流水线数据路径的新的控制器,这种设计提供了高水平的API和FPGA编程。控制器在处理器的设计中加上了多线程和网络,还有SIDM处理。FPGA实现高精度浮点运算是基于RUMP算法的有效实现的基础上的,RUMP算法是计算两个向量的点乘,其精度和运用包括不标准素数的单精度操作的双精度处理器。基于FPGA的处理器的性能超过了浮点DSP机。本设计提供了对FPGA的浮点系统的真实估计。     

基于SOPC的可重构运动控制平台

用于现代运动控制领域的控制器,既需具备强大的计算能力来满足速度和精度的要求,还需具备可重构性能,以便更改或添加新功能.本文提出一种可重构运动控制平台的设计方法,本设计利用可编程片上系统(SOPC)技术,为提高计算能力,用浮点数字信号处理器(DSP)代替片上定点处理器.软件采用基于多线程的框架,比单线程的架构更具柔性.在SOPC Builder工具下对功能模块进行重新组合,可对现场可编程门阵列(FRGA)系统进行快速配置以适应新的功能需求.从算法和功能上来说,该平台具有较好的可重构性,通过对三轴铣床的控制,证明了该设计方法的可行性.     

Noise degradation system using Wiener filter and CORDIC based FFT/IFFT processor

On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology was embraced for expanding the execution of the system. The proposed Wiener filter was planned in such an approach to evacuate the iteration issues in ordinary Wiener filter. The division process was supplanted by a productive inverse and multiplication process in the proposed design. An enhanced design for matrix inverse with reduced computation complexity was executed. The wide-ranging framework processing was focused around IEEE-754 standard single precision floating point numbers. The Wiener filter and the entire system design was integrated and actualized on VIRTEX 5 FPGA stage and re-enacted to approve the results in Xilinx ISE 13.4. The results show that a productive decrease in power and area is developed by adjusting the proposed technique for speech signal noise degradation with latency of n/2 clock cycles and substantial throughput result per every 12 clock cycles for n-bit precision. The execution of proposed design is exposed to be 31.35% more effective than that of prevailing strategies.     

高速定点快速傅立叶变换处理器的设计与实现

针对宽带正交频分复用(OFDM)系统中高速数据处理的要求,提出了64点高速定点快速傅立叶变换(FFT)处理器在现场可编程门阵列(FPGA)中的设计与实现方法.该方法采用了基于按频率抽取(DIF)Radix-4算法的3级流水线结构,每级将乘法器的旋转因子输入端固定为常数值,而不是作为变量从ROM中读取,流水寄存中间数据结果,使之处于稳态,并进行比特位截取定点操作.实验结果表明,该方法在保证运算精度和实现复杂度的同时,减少了ROM读取时间,提高了处理器的数据时钟频率和处理速度,更好的满足了宽带OFDM系统高速数据收发处理的要求.     

Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture

A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules: radar system timer, binary phase coded pulse compression(PC), moving target detection(MTD), constant false alarm rate(CFAR) and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios II CPU is used for target dots combination and false sidelobe target removing. System on programmable chip(SOPC) technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simulation result is given.     

Multiprocessing and Dataflow Processing Architecture of a Pixel Processor and Its VHDL Simulation Strategy

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高性能二维FFT信号处理器

文中给出了一种利用ＴＭＳ３２０Ｃ４０实现二维ＦＦＴ的高速信号处理器，介绍了矢量基二维ＦＦＴ算法在设计时的应用，讨论了信号处理器的设计并给出了利用ＴＭＳ３２０Ｃ４０仿真器完成的软件仿真测试结果。     

新型燃料电池内阻测试仪的研究与设计

针对传统的燃料电池内阻测试方法测试速度慢、测试精度低和测量数据较少的现状,设计了一种基于高频阻抗测量法并具有测试速度快、精度高等特性的燃料电池内阻测试仪。在设计的测试仪中,使用了高精度的程控交流激励源提供信号激励,采用高精度测量单元进行数据测量,并使用浮点的FFT算法对数据进行频谱分析,得到了较好的测量效果。     

集成产品设计多视图建模问题研究

研究了集成产品设计的概念和体系结构 ,对集成产品设计中的产品、功能、组织、工作流、资源和约束视图的描述及主要建模方法进行了探讨。本文的研究工作对建立集成产品设计的过程模型 ,并对这一复杂系统进行过程管理具有一定意义     

基于FPGA的1024点快速傅里叶处理器设计

在对基-2FFT算法原理进行初步分析的基础上,设计了一种1 024点FFT处理器,在基于Xilinx公司的FPGA芯片的基础上,进行了控制单元、数据存储单元、选择因子生成单元和蝶形运算单元的设计.采用verilog HDL语言编程,在ISE平台上编译,利用modelsim软件进行仿真测试.测试结果表明该1 024点FFT处理器在时钟频率为100MHz情况下,处理时间为51.9μs,对于基-2处理器结构,已达到较高的运算速度.     

Terminal Angular Constraint Integrated Guidance and Control for Flexible Hypersonic Vehicle with Dead-Zone Input Nonlinearity

This paper presents an integrated guidance and control model for a flexible hypersonic vehicle with terminal angular constraints. The integrated guidance and control model is bounded and the dead-zone input nonlinearity is considered in the system dynamics. The line of sight angle, line of sight angle rate, attack angle and pitch rate are involved in the integrated guidance and control system. The controller is designed with a backstepping method, in which a first order filter is employed to avoid the differential explosion. The full tuned radial basis function(RBF) neural network(NN) is used to approximate the system dynamics with robust item coping with the reconstruction errors, the exactitude model requirement is reduced in the controller design. In the last step of backstepping method design, the adaptive control with Nussbaum function is used for the unknown dynamics with a time-varying control gain function. The uniform ultimate boundedness stability of the control system is proved. The simulation results validate the effectiveness of the controller design.     

小型无人机GPS／航程推算组合导航系统研究

探讨了在无人机上发展ＧＰＳ／航程推算自式组合导航系统的必要性和可行性；对利用ＧＰＳ定位信息进行导航时所需的坐标转换问题作了分析研究；并对研制的ＧＰＳ／航程推逄组合导航系统的设计思想，总体方案，工作原软硬件结构作了介绍，给出了在小型无人机上进行导航试验的结果。