Algorithmic aspects of area-efficient hardware/software partitioning

Area efficiency is one of the major considerations in constraint aware hardware/software partitioning process. This paper focuses on the algorithmic aspects for hardware/software partitioning with the objective of minimizing area utilization under the constraints of execution time and power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the method devised for solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution for small-sized problems. Simulation results show that the proposed heuristic algorithm yields very good approximate solutions while dramatically reducing the execution time.     

Algorithmic aspects for multiple-choice hardware/software partitioning

Hardware–software partitioning (HW/SW) divides an application into software and hardware. It is one of the crucial steps in embedded system design. For a given task, hardware with different areas may provide different execution speeds due to the potential of parallel execution in hardware implementation. Thus, one task may have multiple-choice in hardware implementation according to the available hardware areas. Existing HW/SW partitioning approaches typically consider only a single implementation manner in hardware, overlooking the multiple-choice of hardware implementations. This paper presents a computing model to cater for the HW/SW partitioning problems with the multiple-choice implementation in hardware. An efficient heuristic algorithm is proposed to rapidly generate approximate solution, that is further refined by a tabu search algorithm also customized in this paper. Moreover, a dynamic programming algorithm is proposed for the exact solution of the relatively small problems. Extensive simulation results show that the approximate solutions are very close to the exact ones, and they can be refined by tabu search to the solutions with the error no more than 1.5% for all cases considered in this paper.     

Finding optimal hardware/software partitions

Most previous approaches to hardware/software partitioning considered heuristic solutions. In contrast, this paper presents an exact algorithm for the problem based on branch-and-bound. Several techniques are investigated to speed up the algorithm, including bounds based on linear programming, a custom inference engine to make the most out of the inferred information, advanced necessary conditions for partial solutions, and different heuristics to obtain high-quality initial solutions. It is demonstrated with empirical measurements that the resulting algorithm can solve highly complex partitioning problems in reasonable time. Moreover, it is about ten times faster than a previous exact algorithm based on integer linear programming. The presented methods can also be useful in other related optimization problems.     

Exploring optimal solution to hardware/software partitioning for synchronous model

Computer aided hardware/software partitioning is one of the key challenges in hardware/software co-design. This paper describes a new approach to hardware/software partitioning for a synchronous communication model including multiple hardware devices. We transform the partitioning into a reachability problem of timed automata. By means of an optimal reachability algorithm, the optimal solution can be obtained with limited resources in hardware. To relax the initial condition of the partitioning for optimization, two algorithms are designed to explore the dependency relations among processes in the sequential specification. Moreover, we propose a scheduling algorithm to improve the synchronous communication efficiency further after partitioning stage. Some experiments are conducted with the model checker UPPAAL to show our approach is both effective and efficient. Jifeng He: On leave from East China Normal University. The work is partially supported by the 973 project 2002CB312001 of the ministry of science and technology, and the 211 project of the ministry of Education of China. Partially Supported by National Natural Science Foundation of China (No.60173003) Received November 2004 Revised July 2005 Accepted August 2005 by Eerke A. Boiten, John Derrick, Graeme Smith and Ian Hayes     

三种软硬件划分算法的比较分析

软硬件划分是嵌入式系统软硬件协同设计中的关键技术之一,如何兼顾系统的性能和成本,达到两者的最佳结合,是软硬件划分的主要问题.针对单CPU多ASICs类型的目标结构,选取了遗传算法、禁忌搜索算法和模拟退火算法等全局优化算法进行系统的软硬件划分,并对3种算法的有效性进行了比较分析.     

嵌入式系统软硬件自动划分方法研究

软硬件划分一直是嵌入式系统软硬件协同设计中的难点,如果离开具体系统,单纯的软硬件划分,其性能很难评估。本文提出基于系统体系结构,应用遗传算法来进行多目标优化的软硬件自动划分方法。在具体设计中,使用数据流图对系统建模,采用邻接表进行个体编码,定义交叉、变异操作,同时引入小生境技术,保持解的多样性。该方法为嵌入式系统软硬件自动划分提供一种新思路。     

Acceleration of software algorithms using hardware/software co-design techniques

Currently there is significant interest in the design and implementation of embedded systems where the hardware and software subsystems are developed concurrently in order to meet design constraints. We present a development environment for general-purpose systems, where the objective is to accelerate the performance of software-based applications, which are specified by C programs. Such programs may be partitioned into hardware and software subsystems — a speed-critical region of the software is implemented in an FPGA in order to provide the performance acceleration. We also discuss two versions of the underlying system hardware architecture. Practical examples are given to illustrate our approach.     

基于自适应蚁群算法的软硬件划分

为了更好地解决软硬件双路划分问题,提出一种自适应蚁群算法．基本思想是：对状态转移概率与信息素挥发因子,采取自适应调节策略．保证了算法前期蚁群的随机性较大,可以充分全局搜索;算法后期蚁群的随机性降低,以使算法在较短的时间内收敛．对不同节点的控制数据流图进行仿真实验,表明在同等条件下,相对于改进模拟退火、改进禁忌搜索、改进蚁群算法以及ＤＣＧ３Ａ 方法,所提出算法的命中率与收敛时间结果均更优．节点规模越大,优势尤其明显．     

Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms

In this contribution we present a new paradigm and methodology for the Network-on-chip (NoC) based design of complex hardware/software systems. While classical industrial design platforms represent dedicated fixed architectures for specific applications, flexible NoC architectures open new degrees of system reconfigurability. After giving an overview on required demands for NoC hyper-platforms, we describe the realisation of these prerequisites within the HiNoC platform. We introduce a new dynamic hardware/software co-design methodology for pre- and post-manufacturing design. Finally we will summarize the concept combined with an outlook on further investigations.     

A dynamic programming algorithm for tree-like weighted set packing problem

In hierarchical organizations, hierarchical structures naturally correspond to nested sets. That is, we have a collection of sets such that for any two sets, either one of them is a subset of the other, or they are disjoint. In other words, a nested set system forms a hierarchy in the form of a tree structure. The task assignment problem on such hierarchical organizations is a real life problem. In this paper, we introduce the tree-like weighted set packing problem, which is a weighted set packing problem restricted to sets forming tree-like hierarchical structure. We propose a dynamic programming algorithm with cubic time complexity.     

Leveraging cost matrix structure for hardware implementation of stereo disparity computation using dynamic programming

Dynamic programming is a powerful method for solving energy minimisation problems in computer vision, for example stereo disparity computations. While it may be desirable to implement this algorithm in hardware to achieve frame-rate processing, a na?¨ve implementation may fail to meet timing requirements. In this paper, the structure of the cost matrix is examined to provide improved methods of hardware implementation. It is noted that by computing cost matrix entries along anti-diagonals instead of rows, the cost matrix entries can be computed in a pipelined architecture. Further, if only a subset of the cost matrix needs to be considered, for example by placing limits on the disparity range (include neglecting negative disparities by assuming rectified images), the resources required to compute the cost matrix in parallel can be reduced. Boundary conditions required to allow computing a subset of the cost matrix are detailed. Finally, a hardware solution of Cox’s maximum-likelihood, dynamic programming stereo disparity algorithm is implemented to demonstrate the performance achieved. The design provides high frame rate (>123 fps) estimates for a large disparity range (e.g. 128 pixels), for image sizes of 640 × 480 pixels, and can be simply extended to work well over 200 fps.     

A hardware Memetic accelerator for VLSI circuit partitioning

During the last decade, the complexity and size of circuits have been rapidly increasing, placing a stressing demand on industry for faster and more efficient CAD tools for VLSI circuit layout. One major problem is the computational requirements for optimizing the place and route operations of a VLSI circuit. Thus, this paper investigates the feasibility of using reconfigurable computing platforms to improve the performance of CAD optimization algorithms for the VLSI circuit partitioning problem. The proposed Genetic algorithm architecture achieves up-to 5× speedup over conventional software implementation while maintaining on average 88% solution quality. Furthermore, a reconfigurable computing based Hybrid Memetic algorithm improves upon this solution while using a fraction of the execution time required by the conventional software based approach.     

Convex regularization-based hardware/software co-design for real-time enhancement of remote sensing imagery

In this paper, we address a new approach for high-resolution reconstruction and enhancement of remote sensing (RS) imagery in near-real computational time based on the aggregated hardware/software (HW/SW) co-design paradigm. The software design is aimed at the algorithmic-level decrease of the computational load of the large-scale RS image enhancement tasks via incorporating into the fixed-point iterative reconstruction/enhancement procedures the convex convergence enforcement regularization by constructing the proper projectors onto convex sets (POCS) in the solution domain. The established POCS-regularized iterative techniques are performed separately along the range and azimuth directions over the RS scene frame making an optimal use of the sparseness properties of the employed sensor system modulation format. The hardware design is oriented on employing the Xilinx Field Programmable Gate Array XC4VSX35-10ff668 and performing the image enhancement/reconstruction tasks in a computationally efficient parallel fashion that meets the near-real time imaging system requirements. Finally, we report some simulation results and discuss the implementation performance issues related to enhancement of the real-world RS imagery indicative of the significantly increased performance efficiency gained with the developed approach.

A dynamic software release model

The determination of optimal software release times constitutes an interesting decision making problem which involves the stochastic structure of the underlying software reliability model, as well as various cost parameters. There is an apparent tradeoff between testing the software further to improve its reliability, and releasing it for operational use to decrease the costs. We propose and analyze in depth a new dynamic model with sufficient generality. After each failure, a debugging activity, possibly imperfect, is undertaken and a decision is made regarding the duration of additional testing. If no failure is observed during this time, then the software is released. Otherwise, the failure is debugged and the decision process is repeated in a dynamic fashion. The problem is formulated using dynamic programming and interesting characterizations of the optimal release policy are presented. The dynamic solution procedure is demonstrated by some numerical illustrations.     

A hardware/software partitioning algorithm based on artificial immune principles

Hardware/software codesign is the main approach to designing the embedded systems. One of the primary steps of the hardware/software codesign is the hardware/software partitioning. A good partitioning scheme is a tradeoff of some constraints, such as power, size, performance, and so on. Inspired by both negative selection model and evolutionary mechanism of the biological immune system, an evolutionary negative selection algorithm for hardware/software partitioning, namely ENSA-HSP, is proposed in this paper. This ENSA-HSP algorithm is proved to be convergent, and its ability to escape from the local optimum is also analyzed. The experimental results demonstrate that ENSA-HSP is more efficient than traditional evolutionary algorithm.     

A dynamic programming algorithm for days-off scheduling with sequence dependent labor costs

This paper presents a dynamic programming (DP) algorithm for solving a labor scheduling problem with several realistic days-off scheduling constraints and a cost structure that depends on the work sequence for each employee. The days-off scheduling constraints include the following: (1) each employee is assigned no more than three workdays per week, (2) each employee is assigned at least two consecutive off days per week, and (3) any work stretch cannot exceed four consecutive workdays. The sequence-dependent cost structure assumes that the daily wage of each employee depends on two factors: (1) whether the given workday is weekend or a regular workday, and (2) the sequence of work patterns assigned in previous days. A DP algorithm suited to instances of moderate size is used to determine the optimum work assignments that minimize the total labor cost, while satisfying the work demand under the stated constraints.