An enhanced erase mechanism during channel Fowler-Nordheimtunneling in flash EPROM memory devices

An enhanced erase behaviour observed during the channel Fowler-Nordheim (FN) tunneling erase operation was examined in details. This enhanced erase occurs when a high p-well voltage is used, with the source and drain junctions of the cell left floating, during the erase operation. Our investigation indicates that the floating source and drain take on a high junction voltage during the p-well voltage transient. This causes transient band-to-band tunneling, and in some cases, junction avalanche breakdown, to occur in the source and drain junctions. As a result, hot-hole injection into the floating gate takes place to create this enhanced erase phenomenon     

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal ~400 electrons above a n⁺/p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250°C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 μm process, the area of a bit is 0.315 μm² and 0.188 μm² in 0.25 μm technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications     

Negative-gate to substrate erase transient simulation for flash memory

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. This paper addresses substrate erasing using a negative gate bias voltage based on the approximate solution to Poisson’s equation. Substrate erasing using a negative gate bias voltage is one of the more prevalent ways to erase flash memory in currently available consumer products. Many papers have been published on this topic but rarely present detailed derivations and none using this exact set of equations to model this erasing process.     

The effect of dimensional scaling on the erase characteristics of NOR flash memory

In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim tunneling characteristics due to a coupling ratio variation, resulting in a much broader erase threshold distribution. Theoretical analysis including MEDICI simulations confirms the effects of parasitic capacitance on the erase threshold of NOR flash cells.     

A 5-V-only 16-Mb flash memory with sector erase mode

A 5-V-only 16-Mb CMOS flash memory with sector erase mode is described. An optimized memory cell with diffusion self-aligned drain structure and channel erase are keys to achieving 5-V-only operation. By adopting this erase method and row decoders to apply negative bias, 512-word sector erase can be realized. The auto chip erase time of 4 s has been achieved by adopting 64-b simultaneous operation and improved erase sequence. The cell size is 1.7 μm×2.0 μm and the chip size is 6.3 mm×18.5 mm using 0.6-μm double-layer metal triple-well CMOS technology     

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40 nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3 V/− 0.8 V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.     

Temperature dependant flash memory erase transient simulation (Part I)

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing at ambient and non-ambient temperatures. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. Part I of this paper addresses substrate erase modeling using a simulation based on the solution to Poisson’s equation with temperature as an independent variable. The goal of this paper is to demonstrate the derivation of an accurate erase simulation and show the effects of temperature on the threshold voltage shift during the erase process. Several papers have been published on this topic but fail to present detailed derivations and none using this exact set of equations to model the temperature dependent erasing process.     

Temperature dependant flash memory erase transient simulation (Part II)

We present a detailed and accurate physics based transient simulation for modeling flash memory erasing at ambient and non-ambient temperatures. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. Part 1 of this paper derives the equations used to model substrate erasing. This paper addresses drain erase modeling using a simulation based on the solution to Poisson’s equation with temperature as an independent variable. The goal of this paper is to demonstrate the derivation of an accurate erase simulation and show the effects of temperature on the threshold voltage during the erase process. Several papers have been published on this topic but fail to present detailed derivations and none using this exact set of equations to model the temperature dependent erasing process.     

On the switching mechanism in Rose Bengal-based memory devices

Impedance switching has been observed in many organic devices, but the mechanism is still a matter of debate. Reliable switch devices consisting of an organic layer of Rose Bengal derivatives sandwiched in between indium tin oxide and aluminum electrodes were fabricated. Modifying the chemical nature of the organic layers and visualizing the temperature distribution in the organic memory rule out several mechanisms. It is shown that the memory effect originates from filamentary switching.     

20-Mb/s erase/record flash memory by asymmetrical operation

An asymmetrical recording and erasing operation of Flash memory is proposed where the threshold voltage of erase and record states are set above the thermal equilibrium threshold voltage. The recording rate is made ten times faster by using this method along with two other proposed methods: accurate control of the fastest bit and continuous recording using two memory banks. The erasing rate is also made ten times faster by using large-scale parallel operation made practical by a proposed multiphase word-driving scheme. These proposed circuit technologies will enable 20-Mb/s erase/record Flash memories for use in personal high-definition television (HDTV) movie cameras     

A 90-ns one-million erase/program cycle 1-Mbit flash memory

Describes the design and performance of a 245-mil/sup 2/ 1-Mbit (128K*8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.0- mu m EPROM-base technology, the 15.2- mu m/sup 2/ single-transistor EPROM tunnel oxide (ETOX) cell requires only 42 percent of the area required by the previous 1.5- mu m device. One of the most significant aspects of this 1-Mbit flash memory is the one-million erase/program cycle capability. The 1-Mbit memory exhibits 90-ns read access time while the reprogramming performance gives a 900-ms array erase time and a 10- mu s/byte programming rate. Ample erase and program margins through one-million erase/program cycles are guaranteed by the internal verify circuits. Column redundancy is implemented with the utilization of flash memory cells to store repaired addresses.<>     

An 80-ns 1-Mb flash memory with on-chip erase/erase-verifycontroller

An internal erase and erase-verify control system has been implemented in an electrically erasable, reprogrammable, 80-ns 1-Mb flash memory, which is suitable for in-system reprogram applications. The memory utilizes a one-transistor type cell with a cell area of 10.4 μ². The die area is 32.3 mm². An erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers as well as low-resistance polysilicide word lines and scaled periphery transistors. To realize high-sensitivity, high-speed sense circuits, a pMOS transistor (whose gate is connected to its drain) is used as a load transistor     

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.     

A simple and efficient self-limiting erase scheme for highperformance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells     

A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell

The cause of over-erasure in a two-bit nitride storage flash memory cell is investigated. Extra positive charges accumulated above the n/sup +/ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V/sub t/) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state V/sub t/ distribution, which will reduce overerasure significantly.     

Single-wafer polysilicon engineering for the improvement of over erase in a 0.18-/spl mu/m floating-gate flash memory

A new polysilicon grain engineering technology for the improvement of over erase in 0.18-/spl mu/m floating-gate flash memory has been developed with the use of single-wafer polysilicon processing, which makes it practical to use hydrogen as a process variable. The addition of hydrogen in polysilicon deposition significantly alters the reaction kinetics and produces polysilicon thin film of smooth surface, fine and uniformly distributed grains. Such a micrograin polysilicon possesses show excellent high-temperature stability. The benefits of the micrograin polysilicon are to be demonstrated through its improvement in over erase of a 0.18-/spl mu/m floating-gate flash memory.     

三栅 SuperFlash闪存的耐久性退化机理特性

Write/erase degradation after endurance cycling due to electron trapping events in triple-gate flash memory have been detected and analyzed using a UV erasure method. Different from the commonly degradation phenomenon, write-induced electron trapping in the floating gate oxide, electron trapping in tunneling oxide is observed in triple-gate flash memory. Further, the degradation due to single-electron locally trapping/de-trapping in hornshaped SuperFlash does not occur in the triple-gate flash cell This is because of planar poly-to-poly erasing in the triple-gate flash cell instead of tip erasing in the horn-shaped SuperFlash cell Moreover, by TCAD simulation, the trap location is identified and the magnitude of its density is quantified roughly.     

Comprehensive study on a novel bidirectional tunnelingprogram/erase NOR-type (BiNOR) 3-D flash memory cell

In this paper a recently proposed bidirectional tunneling program/erase (P/E) NOR-type (BiNOR) flash memory is extensively investigated. With the designated localized p-well structure, uniform Fowler-Nordheim (FN) tunneling is first fulfilled for both program and erase operations in NOR-type array architecture to facilitate low power applications. The BiNOR flash memory guarantees excellent tunnel oxide reliability and is provided with fast random access capability. Furthermore, a three-dimensional (3D) current path in addition to the conventional two-dimensional (2D) conduction is proven to improve the read performance. The BiNOR flash memory is thus promising for low-power, high-speed, and high-reliability nonvolatile memory applications