High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

High-density MIM capacitors using Al2O3 andAlTiOx dielectrics

We have investigated the electrical characteristics of Al₂ O₃ and AlTiO_x MIM capacitors from the IF (100 KHz) to RF (20 GHz) frequency range. Record high capacitance density of 0.5 and 1.0 μF/cm² are obtained for Al₂ O₃ and AlTiO_x MIM capacitors, respectively, and the fabrication process is compatible to existing VLSI backend integration. However, the AlTiO_x MIM capacitor has very large capacitance reduction at increasing frequencies. In contrast, good device integrity has been obtained for the Al₂O₃ MIM capacitor as evidenced from the small frequency dependence, low leakage current, good reliability, small temperature coefficient, and low loss tangent     

Effects of Al2O3 Dielectric Cap and Nitridation on Device Performance, Scalability, and Reliability for Advanced High- κ/Metal Gate pMOSFET Applications

A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al₂O₃ layer between the high-k dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiO_propcapped with 9 Aring of thin Al₂O₃obtains a low long-channel Vt of -0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm² /V ldr s at 0.8 MV/cm (92% of universal value), a negligible equivalent- oxide-thickness (EOT) increase of 0.1 Aring (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of -0.7 V. This indicates that thin Al₂O₃obtains caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al₂O₃-capped HfSiO_prop is not favorable because it increases the Vt by 50-140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5-0.8 Aring and the Vt instability by 5-13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, high-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO₂ interface.     

原子层沉积方法制备低温多层Al2O3/TiO2复合封装薄膜的研究

原子层沉积(ALD)方法可以制备出高质量薄膜,被认为是可应用于柔性有机电致发光器件(OLED)最有发展前景的薄膜封装技术之一。本文采用原子层沉积(ALD)技术,在低温(80℃)下,研究了Al₂O₃及TiO₂薄膜的生长规律,通过钙膜水汽透过率(WVTR)、薄膜接触角测试等手段,研究了不同堆叠结构的多层Al₂O₃/TiO₂复合封装薄膜的水汽阻隔特性,其中5 nm/5 nm×8 dyads(重复堆叠次数)的Al₂O₃/TiO₂叠层结构薄膜的WVTR达到2.1×10^-5 g/m²/day。采用优化后的Al₂O₃/TiO₂叠层结构薄膜对OLED器件进行封装,实验发现封装后的OLED器件在高温高湿条件下展现了较好的寿命特性。     

Thermally robust Ta2O5 capacitor for the256-Mbit DRAM

The thermal degradation of the Ta₂ O₅ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta₂O₅ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta₂O₅ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained     

Development of Embedded Three-Dimensional 35-nF/mm2 MIM Capacitor and BiCMOS Circuits Characterization

This paper summarizes the electrical characterization of MIM capacitor realized in three dimensions. Manufacturing of the device is described, as well as an electrical comparison of three dielectrics, Si₃N₄, Al₂O₃, Ta₂O₅ and two deposition methods, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Selecting Al₂O₃ deposited by ALD, high density of 35 nF/mm² is obtained with low leakage current. Statistical measurements put forward the industrial robustness of the device integrated in BiCMOS technology. Three circuits embedding this new device are characterized: a high-pass filter, a voltage-controlled oscillator (VCO), and a phase-locked loop (PLL). They demonstrate excellent performances with significant area and assembly costs savings.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

Performance Improvement of $hbox{Sm}_{2}hbox{O}_{3}$ MIM Capacitors by Using Plasma Treatment After Dielectric Formation

In this letter, we investigate the dependence of the performance of metal-insulator-metal (MIM) capacitors with Sm₂O₃ dielectric on plasma treatment (PT) performed before Sm₂O₃ deposition, after Sm₂O₃ deposition, or both before and after Sm₂O₃ deposition. By performing PT in N₂ ambient (PTN) after Sm₂O₃ dielectric formation, the effective quadratic voltage coefficient of capacitance (VCC) can be reduced from 498 to 234 ppm/V² and the effective linear VCC can be reduced from 742.3 to 172 ppm/V for MIM capacitor with Sm₂O₃ dielectric having a capacitance density of ~ 7.5 fF/mum². The leakage current density at +3.3 V can be reduced from 3.44 10^-7 to 1.60 times 10^-8 A/cm² by performing PTN in both before and after Sm₂O₃ deposition. PTN after dielectric formation is an effective way to improve the performance of high-kappa dielectric MIM capacitors for RF and analog/mixed signal IC applications.     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

Reliable Low-Cost Fabrication of Low-Loss $hbox{Al}_{2}hbox{O} _{3}{:}hbox{Er}^{3+}$ Waveguides With 5.4-dB Optical Gain

A reliable and reproducible deposition process for the fabrication of Al₂O₃ waveguides with losses as low as 0.1 dB/cm has been developed. The thin films are grown at ~ 5 nm/min deposition rate and exhibit excellent thickness uniformity within 1% over 50times50 mm² area and no detectable OH^- incorporation. For applications of the Al₂O₃ films in compact, integrated optical devices, a high-quality channel waveguide fabrication process is utilized. Planar and channel propagation losses as low as 0.1 and 0.2 dB/cm, respectively, are demonstrated. For the development of active integrated optical functions, the implementation of rare-earth-ion doping is investigated by cosputtering of erbium during the Al₂O₃ layer growth. Dopant levels between 0.2-5times10²⁰ cm^-3 are studied. At Er³⁺ concentrations of interest for optical amplification, a lifetime of the ⁴I_13/2 level as long as 7 ms is measured. Gain measurements over 6.4-cm propagation length in a 700-nm-thick Al₂O₃:Er³⁺ channel waveguide result in net optical gain over a 41-nm-wide wavelength range between 1526-1567 nm with a maximum of 5.4 dB at 1533 nm.     

Stack gate PZT/Al2O3 one transistorferroelectric memory

We have developed a single transistor ferroelectric memory using stack gate PZT/Al₂O₃ structure. For the same ~40 Å dielectric thickness, the PZT/Al₂O₃/Si gate dielectric has much better C-V characteristics and larger threshold voltage shift than those of PZT/SiO₂/Si. Besides, the ferroelectric MOSFET also shows a large output current difference between programmed on state and erased off state. The <100 us erase time is much faster than that of flash memory where the switching time is limited by erase time     

A novel self-aligned TiN formation by N2+implantation during two-step annealing Ti-salicidation for submicrometerCMOS technology application

A new technology of self-aligned TiN/TiSi₂ formation using N₂⁺ implantation during two-step annealing Ti-salicidation process has been developed. The formation of TiN was confirmed by RBS analysis. The leakage currents of n⁺/p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi₂ contact is 1.2 nA/cm² at -5 V, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500°C. Thus, TiN formed with this technology process is suggested as a very effective barrier layer between TiSi₂ and Al for submicron CMOS technology applications     

Improved Stability of High-Performance ZnO/ZnMgO Hetero-MISFETs

Improved performance and stability was demonstrated for ZnO/ZnMgO hetero-MISFETs. The MIS gate structures that were formed using either a 50-nm-thick Al₂O₃ or HfO₂ gate dielectric layer were examined by observation of the transfer characteristic hysteresis. A significantly reduced hysteresis of less than 0.1 V was obtained for HfO₂ as compared to that for the Al₂O₃ gate dielectric. By reducing the access resistance, the 1-mum gate devices showed improved transconductance values, as high as 54 mS/mm for Al₂O₃ and 71 mS/mm for HfO₂, which are the highest values ever reported for ZnO-based FETs.     

High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

High quality nanolaminate stacks consisting of five Al₂O₃-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O₂ atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10^-4 A/cm² at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10^-8 A/cm² and 1.82 nm, respectively, after annealing at 950 degC     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

A Program-Erasable High-κ Hf0.3N0.2O0.5 MIS Capacitor With Good Retention

We describe a programmable-erasable MIS capacitor with a single high-k Hf_0.3N_0.2O_0.5 dielectric layer. This device showed a capacitance density of ~6.6 fF/mum², low program and erase voltages of +5 and -5 V, respectively, and a large DeltaV_fb memory window of 1.5 V. In addition, the 25degC data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf_0.3N_0.2O_0.5.     

A stacked capacitor technology with ECR plasma MOCVD(Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSixstorage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO₃ thin films is described, The four-layer RuO₂/Ru/TiN/TiSi_x, storage node configuration allows 500°C processing and fine-patterning down to the 0.20 μm size by electron beam lithography and reactive ion etching. Good insulating (Ba_0.4Sr_0.6)TiO₃ (BST) films with an SiO₂ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1×10^{-/6 A}cm² at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 μm size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 μm² with only the 0.3 μm high-storage electrodes     

Improved gain performance in Yb3+-sensitized Er3+-doped alumina (Al2O3) channel opticalwaveguide amplifiers

Small-signal amplification in short, Yb³⁺-sensitized, Er³⁺-doped alumina (Al₂O₃) channel optical waveguides with high Er³⁺ concentrations is analyzed. Taking into account uniform up conversion, excited state absorption (ESA) from the Er³⁺ metastable level (⁴I_13/2 ), and Yb³⁺→Er³⁺ energy transfer by cross relaxation, the obtainable gain improvements compared to Yb³⁺ -free Er³⁺-doped Al₂O₃ optical waveguides are investigated. The amplifier model is based on propagation and population rate equations and is solved numerically by combining finite elements and the Runge-Kutta algorithm. The analysis predicts that 5-cm long Yb³⁺/Er³⁺ co-doped Al₂O ₃ waveguides show 13-dB net signal gain for 100 mW pump power at λ_p=980 nm     

Two-step annealing technique for leakage current reduction inchemical-vapor-deposited Ta2O5 film

A capacitor technology developed to obtain extremely thin Ta₂ O₅ dielectric film with an effective SiO₂ film thickness down to 3 nm (equivalent to 11 fF/μm²) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta₂ O₅ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O₃) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O₂) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps