Adaptively biased linear transconductor

This paper describes a new circuit topology of a linear transconductor. The conventional differential pair (CDP), with a constant tail current, is linearized by an adaptive biasing scheme , and the only extra elements added to the differential pair are source followers. Compared to the CDP, the proposed circuit achieves similar speed and noise performance, but the common-mode rejection is compromised at the expense of tremendous improvement in linearity. While operating from a 1.8-V power supply in a 0.18-/spl mu/m CMOS process, the simulated variation in g/sub m/ for 1-V/sub p-p/ and 2-V/sub p-p/ differential input is 1.2% and 22%, respectively. Also, the THD performance for a 1-V/sub p-p/, 1-MHz differential sinusoidal input is -65 dB, which is about a 40-dB improvement over the CDP.     

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining this voltage difference and the extracted threshold voltage of a saturated MOSFET which has a negative temperature coefficient. This circuit, implemented in a standard 0.35-μm CMOS process, provides a nominal reference voltage of 1.361 V at 2-V supply voltage. Experimental results show that the temperature coefficient is 36.7 ppm/°C in the range from −20 to 100°C. It occupies 0.039 mm² of active area and dissipates 82 μW at room temperature. With a 0.5-μF load capacitor, the measured noise density at 100 Hz and 100 kHz is 3.6 and 2 5 \textnV/?{\textHz} , 2 5\,{\text{nV}}/\sqrt {\text{Hz}} , respectively.     

A low-noise amplifier with automatic gain control and anticlipping control in CMOS technology

A CMOS low-noise amplifier (LNA) with two variable gain ranges of 6 and 9 dB is presented. Variable gain is realized by using linearized MOS resistive circuits (MRCs) as voltage-controlled resistors. One of these resistors is located in the feedback loop of a transresistance output stage and the other is in the bias current generator of the transconductance input stage. Using compatible lateral bipolar transistors (CLBTs) in the fully differential transconductance input stage, the circuit takes advantage of the linear dependence of transconductance on bias current. The equivalent noise is 14 nV/ square root Hz and free from 1/f noise in the voice band. The circuit was integrated in a 2- mu m CMOS process and has an active area of 0.8 mm/sup 2/.<>     

Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI

Analog computations such as four-quadrant multiplication, linear voltage-to-current conversion and sum-square or difference-square are fundamental for many analog signal processing systems. All these functions can be realized based on the principle of the linearized differential pair using floating-voltage sources. This paper describes an improved practical realization of this principle, which is particularly suited to analog VLSI computational systems. The proposed class-AB analog cells are very compact, exhibit low total harmonic distortion and low nonlinearity, have a wide bandwidth, and are compatible with low-power and low-voltage operation. A mathematical discussion on stability and harmonic distortion of the proposed realization is presented. Both simulated results and measurements from fabricated cell samples in a 0.8-/spl mu/m CMOS process are given. The described circuits operate from a single 2-V power supply.     

High current efficiency single-stage bulk-driven subthreshold-biased class-AB OTAs with enhanced transconductance and slew rate for large capacitive loads

This paper introduces two high-performance single-stage bulk-driven (BD) operational transconductance amplifiers (OTA) in weak-inversion with rail-to-rail input and output voltage ranges suited for the excessively low-voltage of 0.5 V supply. The strategy depends on adopting a modified bulk-driven non-tailed input core to achieve high input core transconductance with a minimum power supply and an enhanced input common-mode range. Moreover, a partial positive feedback loop provides an overall improved DC gain and effective transconductance further. The input core of OTA1, named composite class-AB OTA, comprises two combined non-tailed differential pairs as composite differential pairs. The proposed OTA2, named composite super class-AB BD-OTA, exploits a matched bulk-input Flipped voltage follower (FVF) pair to adaptively bias the input core used in the composite class-AB BD OTA. As a result, a significant increase in large-signal input current to the output side due to super class-AB behavior improves the slew rate. The post-layout simulation results using the Cadence Spectre simulator with UMC 0.18 µm process technology confirm that the proposed OTAs have improved small-signal and large-signal performances over the conventional OTA driving a high capacitive load of 5 nF. The proposed composite class-AB and super class-AB BD OTA deliver 2.29 times, and 3.77 times open-loop DC gain, 10.6 times, and 117 times unity-gain bandwidth with 2 times, and 12.03 times slew rate at the expense of almost 0.52 times and 1.21 times power consumed over conventional counterpart, respectively.

     

CMOS micro-power output stage for integrated voltage references

A CMOS micro-power, class-AB output stage with high current-drive capability for integrated voltage references is presented. A weak-inversion MOS translinear-loop ensures that the harmonic mean of the push and pull currents equals a constant bias current. It can source/sink 20 mA with only 15 /spl mu/A quiescent current, thus achieving very high power efficiency. It operates from a 2.5 V power supply and is stable for capacitive loads up to 2 nF.     

A rail-to-rail amplifier input stage with /spl plusmn/0.35%g/sub m/ fluctuation

A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant g/sub m/ is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-/spl mu/m process. The resulting differential pair had a constant transconductance that varied by only /spl plusmn/0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of /spl plusmn/1.5V, resulting in only /spl plusmn/1% fluctuation in g/sub m/ for input common modes from -2 to 2 V.     

A 5 GHz Differential Colpitts CMOS VCO Using the Bottom PMOS Cross-Coupled Current Source

A low phase noise differential Colpitts voltage- controlled oscillator (VCO) with the bottom series PMOS cross-coupled current source is presented. The core Colpitts VCO adopts a pair of PMOS as the biased current source at the bottom, instead of a conventional NMOS topology, to achieve a better phase noise performance as the PMOS has lower flicker and white noise than those of NMOS and the output power spectral density of PMOS operated in bottom-biased type is further less than that in top-biased one in the same power consumption. The fabricated VCO operates from 4.9 to 5.46 GHz with 10.6% tuning range when the power consumption is below 6.4 mW with a supply voltage of 1.8 V. The measured phase noise at 100 kHz offset is $-$100.3 dBc/Hz at 5.46 GHz and achieves a good FOM performance of $-$187 dBc/Hz.      

Millimetre-wave VCO with enhanced f/sub trans/

A 60 GHz voltage-controlled oscillator (VCO) with a double cross-coupled negative-resistance cell is presented. The proposed double cross-coupled pair shows higher f_trans and lower input capacitance than a typical capacitive-degeneration cross-coupled pair at millimetre-wave band. The 60 GHz double cross-coupled VCO has phase noise of -84 dBc/Hz at 100 kHz offset from 59.2 GHz and good FOM of -188 dBc/Hz.     

Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz

An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement.     

High performance QVCO design with series coupling in CMOS technology

A high performance quadrature voltage-controlled oscillator（QVCO） is presented.It has been fabricated in SMIC 0.18μm CMOS technology with top thick metal.The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation.Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise.A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO.The measured phase noise of the proposed QVCO achieves phase noise of-123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz,while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply.The QVCO can operate from 4.09 to 4.87 GHz（17.5%）.Measured tuning gain of the QVCO(K_vco) spans from 44.5 to 66.7 MHz/V.The chip area excluding the pads and ESD protection circuit is 0.41 mm².     

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noiseupconversion minimization

A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f³ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f³ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-μm BiCMOS process, using only MOS active devices     

A CMOS nested-chopper instrumentation amplifier with 100-nV offset

A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV/√Hz consuming a total supply current of 200 μA     

Design of a differential distributed amplifier and oscillator using close-packed interleaved transmission lines

The design of a differential distributed amplifier using close-packed transmission lines is discussed along with the implementation of a differential distributed oscillator. Efficient layout techniques for the implementation of these circuits are demonstrated. A differential distributed amplifier with 25 GHz of bandwidth and 7.5 dB of gain is presented as a design example. The amplifier can also be configured as a 9.2 GHz distributed oscillator with -6 dBm single-ended output power, phase noise of -103 dBc/Hz at a 1 MHz offset, and a 17% tuning range.     

Hydrogenation by ion implantation for scaled SOI/PMOS transistors

Hydrogenation by ion implantation has been investigated as a promising technique for VLSI/SOI and has been correlated with the resultant characteristics of silicon-on-insulator (SOI) PMOS transistors fabricated in Polycrystalline silicon. SOI/PMOS ON currents increase by one order of magnitude and OFF currents decrease by two orders of magnitude. Hydrogenation improves weak-inversion slopes by nearly an order of magnitude. Channel-length scaling does not adversely affect leakage currents in SOI/PMOS devices in hydrogenated fine grain polysilicon down to a channel length of 2 µm on the mask, whereas devices in laser recrystallized polysilicon do show a degradation. SOI/PMOS transistors can be expected to replace resistors as load elements for 256K SRAM's.     

Design issues in CMOS differential LC oscillators

An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors     

A 1-V 3.8 - 5.7-GHz wide-band VCO with differentially tuned accumulation MOS varactors for common-mode noise rejection in CMOS SOI technology

In this paper, a 1-V 3.8 - 5.7-GHz wide-band voltage-controlled oscillator (VCO) in a 0.13-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. This VCO features differentially tuned accumulation MOS varactors that: 1) provide 40% frequency tuning when biased between 0 - 1 V and 2) diminish the adverse effect of high varactor sensitivity through rejection of common-mode noise. This paper shows that, for differential LC VCOs, all low-frequency noise such as flicker noise can be considered to be common-mode noise, and differentially tuned varactors can be used to suppress common-mode noise from being upconverted to the carrier frequency. The noise rejection mechanism is explained, and the technological advantages of SOI over bulk CMOS in this regard is discussed. At 1-MHz offset, the measured phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3 - 2.7-mW, depending on the center frequency, and the buffered output power is -9 dBm. Due to the noise rejection, the VCO is able to operate at very low voltage and low power. At a supply voltage of 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

47 GHz VCO with low phase noise fabricated in a SiGe bipolarproduction technology

A low-phase-noise and low-cost millimeter-wave voltage-controlled oscillator (VCO) has been fully integrated in commercial SiGe bipolar technologies. By varying the bias voltage of the on-chip varactor, the frequency can be continuously tuned from 43.6 to 47.3 GHz. In this frequency range, single-sideband phase noise between -103 and -108.5 dBc/Hz at 1 MHz offset frequency was measured. The output voltage swing of the differential circuit is about 0.85 V_p-p for the single-ended and 1.7 V_p-p for the differential output     

Millimeter-wave VCOs with wide tuning range and low phase noise, fully integrated in a SiGe bipolar production technology

Millimeter-wave voltage-controlled oscillators (VCOs) are presented which are fully integrated in a SiGe bipolar production technology. The low-cost differential circuits have been designed and optimized for low phase noise and wide tuning range. As an example, by varying the bias voltage of the on-chip varactor, the oscillation frequency can be changed from 36 to 46.9 GHz (i.e., by 26%). In this wide frequency range, phase noise between -107 and -110dBc/Hz at 1-MHz offset frequency and single-ended voltage swing of about 0.95V/sub pp/ /spl plusmn/10% (differential: 1.9V/sub pp/) were measured. The circuit consumes 280mW at -5.5-V supply voltage. The high oscillation frequency and low phase noise at wide tuning range are record values for fully integrated oscillators in Si-based technologies. The basic oscillator was then extended by a cascode stage as an output buffer. Now the VCO performance is no longer degraded if nonperfectly terminated transmission lines are driven. Thus, the chip can be mounted in a low-cost socket; however, at the cost of increased phase noise and power consumption.