共查询到18条相似文献,搜索用时 171 毫秒
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提出一种多等位环(multiple equipotential rings,MER)的高压屏蔽新结构MER-LDMOS,并解释了该结构的屏蔽机理,通过2D器件模拟验证了屏蔽机理的正确性.讨论了p-top剂量、等位环长度、等位环间距以及氧化层厚度对MER-LDMOS击穿电压的影响.结果表明MER-LDMOS突破常规LDMOS高压屏蔽的能力,击穿电压较常规LDMOS提高一倍以上;同时,该结构具有工艺简单、工艺容差大、反向泄漏电流小等优点,为高压集成电路中高压屏蔽的问题提供了一种新的解决方案. 相似文献
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针对衬底辅助耗尽效应降低常规super junction LDMOS(SJ-LDMOS)击穿电压的不足,提出了一种新的具有部分n埋层的高压SJ-LDMOS器件结构.通过该部分n埋层,不仅补偿了由于衬底辅助效应所致的电荷不平衡现象,实现了高的击穿电压,而且该埋层在器件正向导通时为电流提供了辅助通道,减小了器件导通电阻.分析了器件结构参数和参杂对器件击穿电压和导通电阻的影响,结果表明文中所提出的新结构具有高的击穿电压、低的导通电阻以及较好的工艺容差等特性.此外,该结构与智能功率集成技术兼容. 相似文献
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具有部分n埋层的高压SJ-LDMOS器件新结构 总被引:1,自引:0,他引:1
针对衬底辅助耗尽效应降低常规super junction LDMOS(SJ-LDMOS)击穿电压的不足,提出了一种新的具有部分n埋层的高压SJ-LDMOS器件结构.通过该部分n埋层,不仅补偿了由于衬底辅助效应所致的电荷不平衡现象,实现了高的击穿电压,而且该埋层在器件正向导通时为电流提供了辅助通道,减小了器件导通电阻.分析了器件结构参数和参杂对器件击穿电压和导通电阻的影响,结果表明文中所提出的新结构具有高的击穿电压、低的导通电阻以及较好的工艺容差等特性.此外,该结构与智能功率集成技术兼容. 相似文献
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三端自由高压LDMOS器件设计 总被引:3,自引:0,他引:3
应用RESURF原理,设计了三端自由的高压LDMOS器件。采用虚拟制造技术,分析比较了多种结构,对器件结构进行了优化。设计了与常规CMOS兼容的高压器件结构的制造方法和工艺。采用虚拟制造,得到NMOS和PMOS虚拟器件,击穿电压分别为350V和320V。 相似文献
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对600V以上级具有高压互连线的多区双RESURF LDMOS击穿特性进行了实验研究,并对器件进行了二维、三维仿真分析.利用多区P-top降场层的结终端扩展作用以及圆形结构曲率效应的影响,增强具有高压互连线的横向高压器件漂移区耗尽,从而降低高压互连线对器件耐压的影响.实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与P-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有高压互连线的高压器件击穿特性.在不增加掩模版数、采用额外工艺步骤的条件下,具有30μm高压互连线宽度的多区双RESURF LDMOS击穿电压实验值为640V.所设计的高压互连器件结构可用于电平位移、高压结隔离终端,满足高压领域的电路设计需要. 相似文献
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对600V以上级具有高压互连线的多区双RESURF LDMOS击穿特性进行了实验研究,并对器件进行了二维、三维仿真分析.利用多区P-top降场层的结终端扩展作用以及圆形结构曲率效应的影响,增强具有高压互连线的横向高压器件漂移区耗尽,从而降低高压互连线对器件耐压的影响.实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与P-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有高压互连线的高压器件击穿特性.在不增加掩模版数、采用额外工艺步骤的条件下,具有30μm高压互连线宽度的多区双RESURF LDMOS击穿电压实验值为640V.所设计的高压互连器件结构可用于电平位移、高压结隔离终端,满足高压领域的电路设计需要. 相似文献
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600伏高压LDMOS的实现 总被引:3,自引:2,他引:1
综合利用RESURF技术、内场限环技术及双层浮空场板技术,充分降低高压LDMOS的表面电场,使用常规低压工艺,最终实现600伏高压LDMOS。本文介绍了此高压LDMOS的设计方法、器件结构、制造工艺和测试结果。 相似文献
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使用专门设计的LDMOS高压器件,实现了一个具有高压驱动能力(±150 V)和大增益(>80 dB)的CMOS运算放大器。模拟结果显示,N沟道和P沟道LDMOS晶体管的最大击穿电压都超过了320 V,高压隔离超过300 V,从而可以确保其高压放大功能。该运算放大器适用于数字通信,如程控交换机中的高压驱动电路的单片集成。 相似文献
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《Microelectronics Reliability》2014,54(12):2704-2716
The reduction of breakdown voltage (BV) influenced by high voltage interconnection (HVI) is a key problem in power integrated circuit, which essentially is that the modulation of electric field distribution at the device surface caused by HVI. In this paper, we review the developments of the methods to shield HVI including thick insulating film technology, field reduction layer technology, field plate technology and self-shielding technology. The four kinds of HVI technologies prevent BV degradation from the introduced adverse charge induced by interconnections in different ways. Thick insulting film technology increases the distance between the HVI and surface of silicon. Field reduction layer technology uses additional doping layers with optimized impurity concentration to enhance the depletion of the drift region under HVI. Field plate technology shields the influence of HVI with various field plate structures. Self-shielding technology makes HVI avoid crossing over high voltage junction terminal (HVJT), thus no additional shielding structure is needed. The divided reduced surface field (RESURF) technology solves the leakage current in the self-shielding structure. 相似文献
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A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure. 相似文献
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Wing-Shan Tam Sik-Lam Siu Oi-Ying Wong Chi-Wah Kok Hei Wong V. Filip 《Microelectronics Reliability》2012,52(8):1645-1650
To achieve a high blocking voltage, a power MOSFET is often guarded with multiple floating field limiting rings (MFFLRs) to re-distribute the electric field for extending the breakdown voltage. However, this high-voltage protecting structure occupies a significant silicon area of the power MOSFET. The breakdown field of a floating ring depends on the junction curvature, sizes of the rings and the spacing between the rings. A good design can reduce the total silicon area of the MOSFET transistor by optimizing the floating ring design through modeling. The conventional approach was based on the classical breakdown field model originally developed for the low-voltage p–n junction which has limited precision in the medium to high electric field range. In this work, a precise fitting model for the MFFLR structure with high junction breakdown voltage is proposed. Measurement results of the breakdown voltage of the MOSFETs for the MFFLR structure are presented. 相似文献
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A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n+-regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n+-regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (E1) and reduce the electric field of the silicon layer (Es), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. EI = 731 V/μm and BV = 750 V are obtained by 2D simulation on a l-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field E1 and reduced field Es by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively. 相似文献