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1.
A cascode modulated CMOS class-E power amplifier (PA) is presented in this paper. It is shown that by applying a modulated signal to the gate of the cascode transistor the output power is modulated. The main advantage of the proposed technique is a high 35 dB output power dynamic range. The peak power added efficiency (PAE) is 35%. The concept of the cascode power control of class-E RF PA operating at 2.2 GHz with 18 dBm output power was implemented in a CMOS technology and the performance has been verified by measurements. The prototype CMOS PA is tested by single tone excitation and by enhanced data rates for GSM evolution (EDGE) modulated signal. Digital predistortion is used to linearize the transfer characteristic. The EDGE spectrum mask is met and the rms error vector magnitude (EVM) is less than 4° in the entire output power range.  相似文献   

2.
In this letter, we present an injection-locked Class-E power amplifier (Class-E ILPA) suitable for 2.4-GHz wireless sensor network applications where the maximum transmit-power is typically about 10dBm. In such a low transmit-power application, it is a great challenge to achieve a high transmit efficiency because the driving power and dc power consumption in the previous stage are no more negligible compared with the transmitted signal power. The proposed Class-E ILPA, which is fully integrated in 0.18-/spl mu/m CMOS technology, achieves the power added efficiency of 44.5% while delivering the output power of 11dBm with drain efficiency of 49.3% at 1.2-V supply voltage. The measured locking range reaches 300MHz with the input driving power of -6dBm.  相似文献   

3.
作为无线电能传输(WPT)系统的核心部件之一,E类功率放大器的理论效率可达100%,具有很好的研究前景。本文对E类功率放大器进行理论分析与设计建模,运用电磁仿真软件ADS进行仿真,通过源牵引和负载牵引进行最佳阻抗匹配以优化效率,基于仿真结果进行了硬件电路设计制作。结果表明,设计制作的E类功放在27~29MHz输出的最大功率附加效率(PAE)为91.3%,同时获得17.5 d B的功率增益,验证了设计的正确性与可行性。  相似文献   

4.
The effects of component variations on a high-Q class-E amplifier are simulated and measured. Design equations are provided for the case of a 50% duty cycle with B at its optimum value for a given R. Six distinct operating points are analyzed for the output network. The problem of tuning a high-Q class-E amplifier is addressed. Normally, it cannot be tuned for maximum output power without degrading efficiency. An auxiliary circuit is added to the design so that it can be tuned for maximum output power in order to achieve optimum efficiency. Measured data are obtained at low frequencies for an amplifier with a loaded Q of 340  相似文献   

5.
许多商业和国防系统应用都需要高效率的微波和射频功率放大器。这些应用包括无线LAN、蜂窝电话、通信系统和先进的机载有源相控阵雷达系统。技术选择、设计方法和制造周期时间是这些系统的主要成本。简单和精确的设计可成功地实现开关方式的S波段E类高效率功率放大器。E类放大器设计是基于采用一个串联或并联的谐振负载网络。在有源器件输出端获得最佳化,使器件的DC功率耗散最小。有源器件作为一个开头由RF输入信号驱动至导通和关断状态。开关晶体管(D、E、F类)的理想AC负载线如图1(B)所示。可见工作点沿着Vds和I ds轴的移动,亦即器…  相似文献   

6.
Class-E amplifiers are attractive for wireless handsets because of their high efficiency and simple implementation. However, it requires inductors in its output matching network that are inherently low Q components affecting efficiency and may require significantly large area in fully integrated implementation. In this paper a novel approach of implementing parallel circuit differential class-E amplifier is presented. Instead of using an inductor parallel to the transistor drain of each amplifier, a single capacitor at the single ended side of the balun provides the parallel inductance effect to the switching transistors. As a result, number of inductors required for circuit implementation is reduced which means reduced losses, less area and better tuning of reactance can be achieved. A test circuit is implemented in 0.13 μm CMOS process. Measurement results verify the validity of the concept. The Power Amplifier achieves 22 dBm output power at 2.4 GHz from a 2.5 V with an overall Power Added Efficiency of 38 %.  相似文献   

7.
This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-μm CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output differential-to-single-ended conversion. At 2-V supply and at 1.98 GHz, the power amplifier achieves 48% power-added efficiency (41% combined with the balun)  相似文献   

8.
In this paper, a class-E power amplifier using four 1-W GaAs MESFET's at 935 MHz is demonstrated using a new extended resonance power-combining technique. A microstrip amplifier based on this technique was designed and fabricated which combines four 1-W Siemens CLY5 GaAs MESFET's with 67% power-added efficiency at 935 MHz  相似文献   

9.
A single stage class-E power amplifier in GaN high electron mobility transistor (HEMT) technology is reported. The circuit operates at 1.9 GHz. At 30-V drain bias, a power-added-efficiency (PAE) of 57% and a maximum output power of over 37dBm was achieved, corresponding to a power density of 5.25W/mm. At 40-V drain bias, an output power of 38.7dBm is achieved at 50% PAE corresponding to a power density of 7.4W/mm.  相似文献   

10.
A 700-MHz fully differential class-E CMOS power amplifier for wireless applications has been built toward maximum efficiency. The prototype can deliver 1 W of output power in a 50-Ω output impedance. The maximum power-added efficiency (PAE) is measured to be 62%. The obtained efficiency and output power is compared with the class-E amplifiers theory  相似文献   

11.
This paper presents a design methodology of a highly efficient power link based on Class-E driven, inductively coupled coil pair. An optimal power link design for retinal prosthesis and/or other implants must take into consideration the allowable safety limits of magnetic fields, which in turn govern the inductances of the primary and secondary coils. In retinal prosthesis, the optimal coil inductances have to deal with the constraints of the coil sizes, the tradeoffs between the losses, H-field limitation and dc supply voltage required by the Class-E driver. Our design procedure starts with the formation of equivalent circuits, followed by the analysis of the loss of the rectifier and coils and the H-field for induced voltage and current. Both linear and nonlinear models for the analysis are presented. Based on the procedure, an experimental power link is implemented with an overall efficiency of 67% at the optimal distance of 7 mm between the coils. In addition to the coil design methodology, we are also presenting a closed-loop control of Class-E amplifier for any duty cycle and any value of the systemQ.  相似文献   

12.
为了有效实现高谐波抑制并提高功率附加效率,提出了一种适用于4G-LTE无线通信系统的高效F类功率放大器。该功率放大器使用了低电压p-HEMT晶体管和小型微带抑制单元,能够在低射频输入功率下产生n次谐波抑制和较高的功率附加效率(power added efficiency,PAE)。采用谐波平衡法对提出的功率放大器进行了仿真分析,并对其进行了实际制造。通过实际测量对仿真结果进行了验证。测量结果显示,提出功率放大器的工作频率为1.8 GHz,带宽为100 MHz,平均PAE为76.9%,且具有2V的极低漏极电压。射频输入功率范围分别为0-12 dBm时,最大输出功率和增益分别为23.4和17.5 dBm。  相似文献   

13.
The continuous class-E power amplifier at sub-nominal condition is proposed in this paper. The class-E power amplifier at continuous mode means it can be high efficient on a series matching networks while at sub-nominal condition means it only requires the zero-voltage-switching condition. Comparing with the classical class-E power amplifier, the proposed design method releases two additional design freedoms, which increase the class-E power amplifier’s design flexibility. Also, the proposed continuous class-E power amplifier at sub-nominal condition can perform high efficiency over a broad bandwidth. The performance study of the continuous class-E power amplifier at sub-nominal condition is derived and the design procedure is summarised. The normalised switch voltage and current waveforms are investigated. Furthermore, the influences of different sub-nominal conditions on the power losses of the switch-on resistor and the output power capability are also discussed. A broadband continuous class-E power amplifier based on a Gallium Nitride (GaN) transistor is designed and testified to verify the proposed design methodology. The measurement results show, it can deliver 10–15 W output power with 64–73% power-added efficiency over 1.4–2.8 GHz.  相似文献   

14.
Gallium Nitride shows huge potential in power electronics applications thanks to the superior intrinsic material properties which result in improved performance both at device level and system level. Great effort has been taken in recent years to industrialize GaN technology and to solve some of the major drawbacks like reliability issues and dynamic effects. The goal of this work is to propose a novel methodology to analyse the role of these phenomena on the end application efficiency. These insights can thus lead to a system-level driven optimization of GaN technology. We propose a method based on T-CAD mixed-mode simulation and we give an example of its implementation in the analysis of a class-E power amplifier for wireless power transfer. Efficiency curve is extracted for different load resistance values. This is carried out for the device both in relaxed and in stressed conditions to evaluate the impact of buffer traps. It is demonstrated how the main degradation resides in the increased dynamic resistance while threshold voltage shift and output capacitance variations both play a minor role. A method to calculate the dynamic resistance evolution during the switching cycles is then outlined. At the design point the resistance is expected to fully recover to the nominal value.  相似文献   

15.
This paper presents an analysis of the effect of duty ratio on power loss and efficiency of the Class-E amplifier. Conduction loss for each Class-E circuit component is derived and total amplifier losses and efficiency are expressed as functions of duty ratio. Two identical 300-W Class-E amplifiers operating at 7.29 MHz are designed, constructed, and tested in the laboratory. Dependence of total efficiency upon duty ratio when using real components is derived and verified experimentally. Derived loss and efficiency equations demonstrate rapid drop in efficiency for low duty ratio (below approximately 30%). Experimental results very closely matched calculated power loss and efficiency.  相似文献   

16.
This paper discusses and illustrates the key device design issues for SiGe BiCMOS HBTs suitable for wireless power amplifier (PA) applications. Experimental results addressing ruggedness, ac performance, and safe operating area for high-breakdown SiGe HBTs built in several generations of BiCMOS technology are presented. Implications of recent high-performance SiGe HBT scaling achievements for BiCMOS technologies targeting wireless PA applications are considered. Circuit results for GSM, PCS, GPRS, and EDGE front-end modules have been obtained. A one-chip solution is demonstrated, including control circuitry and switching functionality, that supports all GPRS, PCS, and EDGE modes featuring output power at 33.8 dBm and overall power added efficiency of 37% withstanding voltage standing wave ratio conditions of 15:1.  相似文献   

17.
The authors present a 1.8 GHz class E power amplifier for wireless communications. A fully integrated class E power amplifier module was designed, fabricated and tested. The circuit was implemented in a self-aligned-gate, depletion mode 0.8 μm GaAs MESFET process. The amplifier delivers 23 dBm of power to the 50Ω load, with a power added efficiency of 57% at a supply voltage of 2.4 V  相似文献   

18.
A power amplifier for wireless applications has been implemented in a standard 0.25-μm CMOS technology. The power amplifier employs class-E topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-E load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50-Ω load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices  相似文献   

19.
20.
Secure transmission of multimedia information (e.g., voice, video, data, etc.) is critical in many wireless network applications. Wireless transmission imposes constraints not found in typical wired systems such as low power consumption, tolerance to high bit error rates, and scalability. A variety of low power techniques have been developed to reduce the power of several encryption algorithms. One key idea involves exploiting the variation in computation requirements to dynamically vary the power supply voltage. Application of low power techniques to a wireless camera application yield more than an order of magnitude reduction in power consumption over conventional design methods. Test circuits for five algorithms have been fabricated in a 0.6 m process and the resulting power consumption of each is presented. In addition, a low power hybrid system that combines a powerefficient keystream generator with a secure pseudorandom seed generator is proposed that provides 1 Mbps data encryption at a total estimated power consumption of 150 W.  相似文献   

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