高动态科学级CMOS相机设计与成像分析

为了满足高动态范围高灵敏度的全局曝光模式下成像系统的需求,基于CIS-2521科学级CMOS图像传感器设计了一个相机系统,通过分析CIS-2521芯片像素读出结构特点,通过芯片内部模拟相关双采样与FPGA片内数字域相关双采样完成相关四采样算法,列向噪声去除效果明显。通过设计曲线拟合双增益通道图像数据合成输出,保证了系统成像有较高输出动态范围。相机常温下输出图像峰值信噪比达62.9dB,采用半导体制冷后输出图像峰值信噪比74.3dB。根据EMVA1288标准实测相机动态范围达到78.2dB,设计的相机系统实现了每秒50帧2 560×2 160像素,16bit深度高清晰度高动态范围图像的实时全局曝光成像输出,能够满足低照度条件下的高帧频高动态范围成像的需求。     

基于4T结构的高灵敏度CMOS图像传感器设计

基于0.35μm工艺,设计了应用于低光照环境下的低噪声、高灵敏度CMOS图像传感器。该图像传感器采用PPD 4T像素结构,像素阵列512×512,包含列级运放、水平移位寄存器、逻辑控制单元、单斜率模数转换器和偏置电路等模块。通过采用低噪声PPD 4T像素结构、低噪声列级放大器电路结构,以及对版图的优化设计等措施实现了低噪声、高灵敏度的CMOS图像传感器设计。     

像素内两次曝光组合的宽动态范围CMOS图像传感器

提出了一种基于五管有源像素的宽动态范围CMOS图像传感器（CIS）,在像素内部的浮动节点处进行长曝光时间信号和短曝光时间信号的组合。通过优化像素操作,光电响应曲线得到了压缩,获得了宽动态范围图像。设计的CMOS图像传感器采用0.18μm CIS工艺进行了流片,测试结果表明在两次曝光时间分别为2.4ms和70ns,30帧每秒的帧频条件下,传感器的动态范围达到80dB,满足安防监视系统的应用需求。     

基于自适应曝光的CMOS图像传感器的设计与实现

从硬件结构、曝光策略和模拟结果入手，在传统滚筒式曝光基础上，通过对用户设定区域像素饱和值的统计和曝光时间选择算法，提出了一种CMOS图像传感器大动态范围自适应曝光的设计。曝光时间可从1ps至65ms，探测光强范围达到10^1～10^6lux，设计将充分发挥现有像素性能，实现快速实时的自适应曝光需求。     

高光谱成像用高帧频CMOS图像传感器北大核心

针对高帧频、全局曝光和光谱平坦等成像应用需求,设计了一款高光谱成像用CMOS图像传感器。其光敏元采用PN型光电二极管,读出电路采用5T像素结构。采用列读出电路以及高速多通道模拟信号并行读出的设计方案来获得低像素固定图像噪声(FPN)和非均匀性抑制。芯片采用ASMC 0.35μm三层金属两层多晶硅标准CMOS工艺流片,为了抑制光电二极管的光谱干涉效应,后续进行了光谱平坦化VAE特殊工艺,并对器件的光电性能进行了测试评估。电路测试结果符合理论设计预期,成像效果良好,像素具备积分可调和全局快门功能,最终实现的像素规模为512×256,像元尺寸为30μm×30μm,最大满阱电子为400 ke^(-),FPN小于0.2%,动态范围为72 dB,帧频为450 f/s,相邻10 nm波段范围内量子效率相差小于10%,可满足高光谱成像系统对CMOS成像器件的要求。     

CMOS图像传感器时序控制方法研究与实现

针对CMOS图像传感器滚筒式曝光模式,研究采用多种曝光时间,实现多线段拟合像素输出特性曲线,扩展传感器的动态范围,并改善其平滑性,提高图像清晰度;应用电源保护环、像素二次采样等方法消噪。电路选用charter 0.35μm工艺,经仿真验证满足设计要求。     

低功耗高动态范围CMOS图像传感器的设计

设计了一种低功耗高动态范围的CMOS图像传感器16×16像素阵列电路,采用条件重置的方法,钟控比较器的低功耗设计及相关时序电路的优化,在扩展CMOS图像传感器的动态范围下,极大地降低了系统的功耗.实验表明,基于标准CSM 0.35μm 2P4M CMOS工艺,用HSPICE仿真,动态范围最大可以达到普通传感器的4倍,在3.3 V下每列功耗仅为6.6μW.     

多分辨率高速线列CMOS图像传感器设计

设计并验证了一款可选分辨率、高速1 024线列CMOS图像传感器。为了优化列总线读出速率,芯片采用总线分割技术以减小总线寄生电容,有效提升了信号读出速率。传感器具有4种可选择分辨率功能,使其具有更高的帧频。设计的芯片采用0.5μm标准CMOS工艺成功流片,验证了设计的正确性。测试结果表明：满阱容量为4.76 Me^-/像素,动态范围为75 dB;在128分辨率下,帧频能达到36 000 frames/s。     

高动态科学级CMOS相机系统的设计

为了满足全局曝光模式下对高动态范围CMOS相机需求,基于CIS-2521sCMOS器件设计出一个相机系统,通过研究CIS-2521芯片像素读出结构特点和全局曝光模式下驱动时序特点,选用FPGA搭载DDR3作为处理架构,在FPGA内部完成了成像参数控制,sCMOS驱动时序,图像数据采集,图像预处理等SOPC片上一体化设计,并对各个模块功能进行了介绍。设计的相机系统进行成像测试,实现了连续输出50帧/s,2 560×2 160像素,14bit有效深度的高清晰度高动态范围图像,基本满足科学级成像条件的需求。     

一种梯度自适应宽动态CMOS图像传感器像素结构

提出了一种梯度自适应的宽动态CMOS图像传感器像素结构。该像素结构采用多路分流设计,改变了3T-APS图像传感器的单线性响应率;根据不同的光照强度自适应调整响应率,在低照度时具有较大的响应率,在高照度时具有较小的响应率,从而增大了像素的动态范围。该像素结构简单,无需额外复杂的控制电路即可实现对光照强度的自适应梯度响应。基于0.18 μm 1P4M SMIC工艺,采用SILVACO TCAD仿真软件进行电路设计和仿真。结果表明,该CMOS图像传感器像素结构电路的动态范围可达到112.36 dB。     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

CMOS图像传感器用像素级双采样存储技术

多次曝光技术是扩展CM O S APS图像传感器动态范围较为有效的方法,但多于两次的曝光,信号处理复杂,使传感器的帧频受到限制,而像素级双采样存储技术将两次曝光采样及图像组合处理在像素内实现,在获得高动态范围的同时,可有效提高图像实时处理的速度,并且可以工作于高速同步曝光模式。     

A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor

In a CMOS image sensor featuring a lateral overflow integration capacitor in a pixel, which integrates the overflowed charges from a fully depleted photodiode during the same exposure, the sensitivity in nonsaturated signal and the linearity in saturated overflow signal have been improved by introducing a new pixel circuit and its operation. The floating diffusion capacitance of the CMOS image sensor is as small as that of a four transistors type CMOS image sensor because the lateral overflow integration capacitor is located next to the reset switch. A 1/3-inch VGA format (640/sup H//spl times/480/sup V/ pixels), 7.5/spl times/7.5 /spl mu/m/sup 2/ pixel color CMOS image sensor fabricated through 0.35-/spl mu/m two-poly three-metal CMOS process results in a 100 dB dynamic range characteristic, with improved sensitivity and linearity.     

Wide dynamic range CMOS image sensor with in-pixel double-exposure and synthesis

A wide-dynamic-range CMOS image sensor (CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion (FD) of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18 μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second (fps).The proposed CMOS image sensor meets the demands of applications in security surveillance systems.     

Research on Column FPN and Black Level Calibration in Large Array CMOS Image Sensor

A technical investigation, research and im-plementation is presented to correct column fixed pattern noise and black level in large array Complementary metal oxide semiconductor (CMOS) image sensor. Through making a comparison among reported solution, and give large array CMOS image sensor design and considerations, according to our previous analysis on non-ideal factor and error source of piecewise Digital to analog converter (DAC) in multi-channels, an improving accurate piecewise DAC with adaptive switch technique is developed. The research theory has verified by a high dynamic range and low column Fixed pattern noise (FPN) CMOS image sensor prototype chip, which consisting of 8320×8320 pixel array was designed and fabricated in 55nm CMOS 1P4M standard process. The chip active area is 48mm×48mm with a pixel size of 5.7μm×5.7μm. The measured results achieved a high intrinsic dynamic range of 75dB, a low FPN and black level of 0.06％, a low photo response non-uniformity of 1.5％ respectively, and an excellent raw sample image taken by the prototype sensor.     

一种新型大动态范围CMOS图像传感器

提出了一种具有新型像素结构的大动态范围CMOS图像传感器,通过调整单个像素的积分时间来自适应不同的局部光照情况,从而有效提高动态范围。设计了一种低延时、低功耗、结构简单的新型pixel级电压比较器及基于可逆计数器的时间-电压编码电路。采用0.6μm DPDM标准数字CMOS工艺参数对大动态范围像素单元电路进行仿真,积分电容电压Vcint与光电流呈良好的线性关系,其动态范围可达126dB。在3.3V供电电压下,单个像元功耗为2.1μW。     

用于视觉假体的新型高动态范围图像传感器像素单元电路设计

针对于视觉假体的应用领域,本文提出了一种新型的高动态范围的CMOS图像传感器(CMOS Image Sensor,CIS)像素单元电路,该电路采用了列共用单元的条件溢出电容和多次积分技术,大大提高了图像传感器的动态范围,同时使其在低光照时保持较高的灵敏度和信噪比,采用了特许半导体公司的0.35μm CMOS工艺参数对该...     

高帧频大动态范围CMOS图像传感器时序控制电路的设计与实现

本文主要论述了CMOS图像传感器时序控制电路的系统设计和实现方法.针对双采样结构的图像传感器,分析了常用的并行式曝光方式和滚筒式曝光方式两种时序控制方法及其具体实现过程,并根据时序控制电路的功能仿真和在FPGA上的验证结果,对二者进行了比较,证明了这两种方法的可行性.     

基于相对比率的高帧频图像采集器设计与实现

为了在机器视觉应用中是实现高动态范围（high dynamic range,HDR）图像采集,提出了一种基于检测像素相对比率的新型图像采集系统。提出的图像采集器使用全差分电路检测信号比,由基于数字计数器的紧凑列并行读出电路捕捉像素的脉冲宽度调制输出。并设计了相应的光电流比检测像素方法,能独立地捕捉局部场景特征。实验结果显示提出的COMS图像传感器性能较好,当标称帧频为9600帧/秒时,提出的32×32像素阵列原型CMOS图像传感器消耗了4 mW的功率;当最大帧频为24000帧/秒时,此图像传感器消耗了6.8 mW的功率。