Submicrometer CMOS device fabrication using an X-ray stepper

CMOS devices with submicrometer minimum features have been fabricated using X-ray/photo hybrid lithography. The device fabrication process utilized thirteen lithography steps, including four X-ray lithography levels, such as local oxidation of silicon (LOCOS) [1], gate, contact, and wiring, that required the most critical dimension control and alignment accuracy. A step and repeat exposure system and a SiNxmembrane mask were used for the X-ray lithography process. The SiNxmembrane mask was improved in its flatness and effective contrast by employing a stress compensating structure and a secondary electron trapping film. As a result, CMOS devices with 0.4-µm effective channel length were fabricated using a single-layer resist process.     

Thin-base bipolar transistor fabrication using gas immersion laserdoping

Gas immersion laser doping (GILD) is used to fabricate the base and emitter regions of narrow-base n-p-n bipolar transistors. The GILD process is unique in that it allows simple fabrication of box-like impurity profiles which can be placed very accurately in the vertical dimension (±100 Å). Transistors with base widths ranging from 700 to 1200 Å and DC forward current gains greater than 50 are fabricated     

The fabrication and characterization of EEPROM arrays on glassusing a low-temperature poly-Si TFT process

The fabrication and optimization of poly-Si thin-film transistors and memory devices on glass substrates at temperatures of 200°C-400°C is described, and the device characteristics and stability are discussed. The devices were formed using PECVD amorphous silicon, silicon dioxide, and silicon nitride films, and the crystallization of the amorphous silicon was achieved with an excimer laser. The performance of 16×16 EEPROM arrays with integrated drive circuits formed using this technology is presented     

Submicrometer salicide CMOS devices with self-aligned shallow/deepjunctions

The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5-μm physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices     

Submicrometer CMOS devices in zone-melting-recrystallized SOI films

CMOS devices with effective channel lengths ranging from 0.7 to 4.0 µm have been fabricated in zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) films prepared by the graphite-strip-heater technique. Low-temperature processing was utilized to minimize dopant diffusion along subboundaries in the films. Both n- and p-channel devices have low leakage current (<0.1-pA/µm channel width) and good subthreshold characteristics. For ring oscillators with a transistor channel length of 0.8 µm, the propagation delay is 95 ps at a supply voltage of 5 V.     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

A novel ultrathin elevated channel low-temperature poly-Si TFT

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 Å) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V_ds=30 V, V_gs=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFT's     

High-performance low-temperature poly-Si TFTs crystallized byexcimer laser irradiation with recessed-channel structure

High-performance low-temperature poly-Si (LTPS) thin-film transistors (TFTs) have been fabricated by excimer laser crystallization (ELC) with a recessed-channel (RC) structure. The TFTs made by this method possessed large longitudinal grains in the channel regions, therefore, they exhibited better electrical characteristics as compared with the conventional ones. An average field-effect mobility above 300 cm²/V-s and on/off current ratio higher than 10⁹ were achieved in these RC-structure devices. In addition, since grain growth could be artificially controlled by this method, the device electrical characteristics were less sensitive to laser energy density variation, and therefore the uniformity of device performance could be improved     

Modeling of Variation in Submicrometer CMOS ULSI Technologies

The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond.     

MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs

A metal-oxide-nitride-oxide-polysilicon (MONOS) memory device fabricated by sequential lateral solidified (SLS) low-temperature polycrystalline silicon (poly-Si) technology on a glass substrate was investigated. The Si protrusions at grain boundaries (GBs) as a result of the SLS process can be well controlled and located along the width direction of the transistor. Protrusions at the GBs are utilized as emitting source to achieve a MONOS memory device with low operation voltage (/spl les/ 20 V), fast program/erase time, and wide V/sub th/ window by field-enhanced channel hot electron injection for programming and field-enhanced band-to-band tunneling-induced hot hole injection for erase. This is the first study to demonstrate a nonvolatile memory device in low-temperature poly-Si thin-film transistor (LTPS TFT) technology, which can be integrated with TFT-liquid crystal display, to reduce power consumption for mobile applications.     

Characteristics of low-temperature poly-Si TFTs on Al/glasssubstrates

The low-temperature poly-Si TFTs described here were fabricated on the Al/glass substrates by anodic oxidation of Al. An Al layer on glass substrates can be used to control threshold voltage, improve stabilities, and suppress the temperature rise due to self-heating. The Al layer on glass, thus assuring the improved reliability of displays, using this type of TFT, effectively suppressed the self-heating effect of poly-Si TFTs on glass. The threshold voltage of a TFT with an Al layer was more stable than that without an Al layer. These results were supported by numerical analysis     

Submicrometer gate fabrication of GaAs MESFET by plasma etching

Dry etching is employed in the direct fabrication of the main part of semiconductor devices. A submicrometer Schottky-barrier gate is constructed for GaAs MESFET's. The gate has a double-metal-layer configuration. The Au top metal layer is first delineated by ion milling with monitoring equipment, i.e., ion microanalyzer. The metal layer in contact with the GaAs substrate is chemically etched in CF4gas plasma. Controlled side etching of the Mo metal produces the submicrometer gate, leaving a wider top metal layer of Au. The amount of side etching deviates less than 0.05 µm and the gate length is reduced to 0.1 µm. No appreciable damage to the GaAs substrate is found as a result of plasma etching. Half-micrometer gate GaAs MESFET's fabricated by this dry etching technique achieved high-gain and low-noise performance in the X-band.     

Low temperature poly-Si thin-film transistor fabrication bymetal-induced lateral crystallization

A new low temperature crystallization method for poly-Si TFTs was developed: Metal-Induced Lateral Crystallization (MILC). The a-Si film in the channel area of a TFT was laterally crystallized from the source/drain area, on which an ultrathin nickel layer was deposited before annealing. The a-channel poly-Si TFTs fabricated at 500°C by MILC showed a mobility of 121 cm²/V·s, a threshold voltage of 1.2 V, and an on/off current ratio of higher than 10⁶ . These electrical properties are much better than TFTs fabricated by conventional crystallization at 600°C     

亚微米CMOS IC中自对准硅化物工艺的研究

自对准硅化钛工艺有许多重要的优点.但也存在栅氧化物的完整性、硅化物桥接短路、pn结损伤、二极管特性退化等问题.文章针对这些问题,在硅化前和硅化后的清洗、硅化的快速退火处理、接触电阻最佳化以及在硅化物上的接触孔腐蚀的选择性等方面进行了改进,有效地解决了问题.     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

Submicrometer electron-beam direct writing technology for 1-Mbit DRAM fabrication

A 1-Mbit DRAM with 0.5-µm minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 µm(σ) and linewidth deviation of 0.018 µm(σ) in the fabrication.     

Hot carrier analysis in low-temperature poly-Si TFTs using picosecond emission microscope

We have investigated the degradation of n-channel thin-film transistors under dynamic stress. Degradation was examined for various pulse parameters such as rising time or frequency. A shortfall time led to a large degradation. This mechanism was analyzed by using a picosecond emission microscope and a device simulator to examine the transient current, experimentally and theoretically, respectively. We have successfully detected emission at the pulse fall edge for the first time. Emission intensity increased with the decrease in pulse fall time. By means of the transient device simulation, transient current corresponding to the gate pulse was obtained. From the comparison between internal field and transient current, hot carrier current generated in the pulse fall was detected for the first time. A reasonable agreement between the data obtained by the emission microscope and those obtained by the device simulator clearly indicates that hot electrons are the dominant cause of degradation under dynamic stress. On the basis of the comparison between experimental and theoretical results, we proposed a model which takes into consideration electron traps in poly-Si.     

XeCl Excimer laser annealing used in the fabrication of poly-Si TFT's

Mo-gate n-channel poly-Si thin-film transistors (TFT's) have been fabricated for the first time at a low processing temperature of 260°C. A 500-1000-A-thick a-Si:H was successfully crystallized by XeCl excimer laser (308nm) annealing without heating a glass substrate. TFT's were fabricated in the crystallized Si film. The channel mobility of the TFT was 180cm²/V.s when the a-Si:H was crystallized by annealing with a laser having an energy density of 200 mJ/cm². This result shows that high-speed silicon devices can be fabricated at a low temperature using XeCl excimer laser annealing.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.