A low-pass biquad derived filter realization

A biquad derived structure employing two Norton (current differencing) amplifiers is presented which requires the minimum number of components. Transfer characteristics of the form K/SUB 1//D(S) and K/SUB 2/(S+/spl omega//SUB n//Q)/D(S) with D(S)=S/SUP 2/+/spl omega//SUB n/S/Q+/spl omega//SUB n//SUP 2/ are realized. Biasing constraints are of major importance in the detailed realization and a typical circuit design is presented along with a discussion of its performance, which is compared with that of others.     

RF power transistor storage time: theory and measurements

Measurements on two types of UHF power transistors are given. The measured charge storage time constants (/spl tau//SUB s/) were 89 ns and 173 ns, effectively `infinite' for most applications. Then t/SUB s/ is essentially independent of /spl tau//SUB s/, and depends mainly on circuit properties: base drive and collector current waveforms. The measured dependence of t/SUB s/ on circuit and transistor parameters is in accordance with analytical predictions. Therefore storage time can be accounted for explicitly in a priori circuit design of RF power amplifiers.     

An 8-bit, 5 ns monolithic D/A converter subsystem

Describes a 5 ns settling time digital-to-analog converter device, which has been designed for use in video speed successive approximation analog to digital converters. The chip includes a precision reference source with a 25 ppm per degree C average temperature coefficient and a high-speed comparator. The successive approximation approach, restricted to low-speed converters until now, has the advantages of low cost and straightforward drive requirements. The achievement of the operating speeds described is dependent both on the circuit techniques used and the process employed. The DAC circuit, unlike most other devices, uses a multiple-matched current source array technique, which leads to a very linear, low glitch output. Without any form of trimming, most functional devices meet a /spl plusmn//SUP 1///SUB 2/ LSB differential and integral linearity specification, and many are /spl plusmn//SUP 1///SUB 4/ LSB or better.     

Logic gates with shaped Josephson junctions

Long (L//spl lambda//SUB j/>5) in-line Josephson junctions, with varying width along the length L of the device, are investigated as logic gates (/spl lambda//SUB j/ being the Josephson penetration depth). The devices realized have an asymmetric threshold characteristic with almost suppressed sidelobes, providing good logic gain and permitting logic fan-in with multiple control lines. Optimum conditions are found for junctions with width varying approximately sinusoidally along the device length. The so-called shaped junctions are incorporated in various flip-flop circuits to evaluate the transfer time and transfer efficiency of loop circuits, and in a self-resetting inverter circuit to demonstrate the feasibility of self-resetting logic. The principle of current steering and the relatively large operating currents (I/SUB G//spl sime/6 mA) make the circuits suitable for medium-speed applications such as in the decode and control logic of a main-memory chip. For a fan-out of four, the minimum circuit delay is 300 ps, resulting in a power-delay product in the order of 3/spl times/10/SUP -15/ J.     

Gigahertz p-channel enhancement silicon m.o.s.f.e.t. with nonoverlapping gate

The technological and electrical parameters of p-channel enhancement silicon m.o.s.f.e.t.s with recessed gates are presented and compared with conventional structures fabricated in a similar manner. In the instance of the nonoverlapping gate the gain-bandwidth product is increased by a factor of about 3. The maximum frequency, as obtained by extrapolation of measurements up to 1 GHz, is f/SUB max//spl ap/3 GHz. If the depletion region of the drain contact is too short to overlap with the gate field, the static characteristics follow a space-charge-limited current-voltage relation. When higher source-drain voltages are applied the normal enhancement-type behavior results but with reverse transconductance y/SUB r/ strongly reduced (by a factor of 8-12 at 1 GHz). A higher circuit stability is obtainable, whereas the parameters y/SUB i/,y/SUB 0/, and y/SUB f/ are only slightly influenced.     

A high precision monolithic current follower

A monolithic bipolar current follower has been developed which can be used in conjunction with commercially available voltage followers to realize a number of electronic functions. It features an output-input resistance ratio R/SUB o//R/SUB i/ of 10/SUP 6/, a 0.2 percent gain accuracy and a 42 MHz bandwidth.     

High-frequency transistor modeling for circuit design

It has been found that certain high-frequency transistor types cannot be modeled accurately over wide frequency ranges with the hybrid pi or high-frequency T models even though reasonable extrinsic elements are added. Modifying the hybrid pi by replacing r/SUB /spl pi//C/SUB /spl pi// with an RC ladder extends the useful frequency range for that model to f/SUB T//2. A computer optimization program is used to determine the appropriate element values for the extended hybrid-pi model. For the 2N918, a two-section ladder gives a 3 : 1 improvement in the usable frequency range of the model.     

Frequency-independent equivalent-circuit model for on-chip spiral inductors

A wide-band physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-/spl Pi/ model accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. Using frequency-independent RLC elements, this new model is fully compatible with both ac and transient analysis. Verification with measurement data from a SiGe process demonstrates accurate performance prediction and excellent scalability for a wide range of inductor configurations.     

Unified field-effect transistor theory including velocity saturation

It is shown that in any kind of field-effect transistor structure, the usual gradual channel approximation solutions developed for v=/spl mu//SUB 0/E also hold in a slightly modified form for v=/spl mu//SUB 0/E/|1+(/spl mu//SUB 0/E/v/SUB s/)| which gives a good approximation to the velocity field relationship in silicon FETs.     

Overall stability factor of linear two-ports in terms of scattering parameters

Stability conditions for linear active two-ports in terms of classical two-port parameters, which include the terminations, have been derived earlier but the analogous result in terms of scattering parameters apparently is not known. It is shown that the stability condition is 1-|r/SUB G/s/SUB 11/|/SUP 2/-|r/SUB L/s/SUB 22/|/SUP 2/ + |r/SUB G/r/SUB L//spl Delta/|/SUP 2/>2|r/SUB G/r/SUB L/|.|s/SUB 12/s/SUB 21/| from which the overall stability factor is derived.     

Feedthrough in emitter-coupled logic circuits

Emitter coupled logic circuits transient noise behavior is examined. The mechanisms and causes of feedthrough are analyzed using, first, approximate expressions and, second, an accurate model. The experimental observations of feedthrough give ample evidence of good agreement between the theoretical and computational results. An accurate appraisal of the causes of feedthrough, such as C/SUB b//SUB e/, C/SUB b//SUB c/, c/SUB i//SUB d/, C/SUB i//SUB t/, C/SUB p/, and C/SUB c//SUB u//SUB s/ determine the main factors that offer scope for improvement.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

Improved Schottky clamped (T/SUP 2/L) circuits

Al-Si Schottky clamped transistors used as fast switching signal devices or in integrated circuits are superior to gold-doped transistors for such parameters as low-level current gain, leakage current I/SUB CO/, and propagation delay t/SUB pd/. A digital application is used to show how some of these parameters can be optimized for a T/SUP 2/L circuit, providing high switching speed (t/SUB pd/ 4 to 5 ns) and a 40-percent better worst-case low-level noise margin than the usual gold-doped T/SUP 2/L circuit.     

Stable voltage reference sources

A family of well-regulated voltage references are shown, which are readily integrable for use with emitter-coupled logic, threshold logic, or linear circuit arrays. By relying on the relatively well-matched characteristics and the temperature tracking of integrated transistors and resistor ratios, the circuit can provide a large range of output fractions of the power supply. The relationships of the circuit components for various output voltages are derived. One circuit configuration gives fractions of the power supply of less than /SUP 1///SUB 2/ while another configuration gives fractions of the power supply greater than /SUP 1///SUB 2/. Limitations of the obtainable fractions are given. Experimental results are shown for each of the two basic circuit configurations and the temperature stability is demonstrated. Well-defined stable voltages are thus derived with a minimum of components and power drain.     

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.     

Feasibility of an ultra-high-speed Josephson multiplier

The authors discuss the design, fabrication, and evaluation of a Josephson multiplier model featuring all-niobium junctions. They designed a 16-bit /spl times/ 16-bit parallel multiplier and fabricated its critical path model consisting of 828 gates. The circuit was designed using modified variable threshold logic (MVTL) OR-gates and single-junction AND gates. These gates consisted of Nb/AlO/SUB x//Nb Josephson junctions, Nb wiring, Mo resistors, and SiO/SUB 2/ insulators. Both the minimum linewidth and junction diameter were 2.5 /spl mu/m. The observed multiplication time using the critical path model was 1.1 ns. The propagation delay due to the interconnecting wiring was estimated to be 0.20 ns, and the longest path of the circuit consisted of 103 gates. Thus the average gate delay in the circuit was estimated to be 8.7 ps/gate. These results point to the possibility of an ultra high-speed multiplier, about five times faster than any semiconductor device.     

Second generation I/SUP 2/L/MTL: a 20 ns process/structure

A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully been designed, characterized, and demonstrated fully functional over a wide current range and the military temperature range of -55 to 125/spl deg/C. Performance is measured using an in-line five-collector gate having one end injector. The gate performed with the following characteristics at 100 /spl mu/A injector current: /spl beta//SUB U//SUP eff//spl ges/4 for all collectors at 25/spl deg/C and /spl ges/2.5 at -55/spl deg/C, /spl alpha//SUB rec///spl alpha//SUB F//spl cong/0.58 and /spl tau/~/SUB d/=18-20 ns from -55 to 125/spl deg/C, and a speed-power product of 1.4 pJ at 25/spl deg/C. At low injector currents, a constant speed-power product of 0.36 pJ at 25/spl deg/ was obtained.     

A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.     

I/SUP 2/L current gain design

A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell.     

An efficient CMOS buffer for driving large capacitive loads

A CMOS class AB high-drive buffer suitable for driving large capacitive and moderate resistive loads is presented. The buffer, designed using 3-/spl mu/m technology, occupies only 100 mils/SUP 2/ of area and dissipates 1.5 mW of DC power from a /spl plusmn/2.5-V supply, yet it is capable of driving a 5000-pF capacitor at over 100-kHz clocking frequency. The buffer achieves good slew rate and fast settling by entering into a high-drive state during slewing and returning to a low-power wide-band state during the settling period. Unconditional stability is attained when C/SUB L//spl ges/100 pF and R/SUB L//spl ges/10 k/spl Omega/. Total harmonic distortion is below 0.5% for over 70% of the full supply range.