A novel uniplanar compact photonic bandgap power plane with ultra-broadband suppression of ground bounce noise

A novel /spl pi/-bridged photonic bandgap (PBG) power/ground planes is proposed with ultra-broadband suppression of the ground bounce noise(GBN) in the high-speed printed circuit boards. The S-parameters of the proposed low-period structures show that the novel uniplanar compact photonic bandgap (UC-PBG) structures could omni-directionally suppress the GBN in RF/analog circuits and digital circuits. The high omnidirectionally suppressions of the GBN for the proposed structure are validated both experimentally and numerically in the noise bandwidth from 300MHz to 6GHz, almost the whole noise band.     

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-V_TH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-V_TH transistors in place of high-V_TH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-V_TH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.     

An electromagnetic crystal power substrate with efficient suppression of power/ground plane noise on high-speed circuits

An electromagnetic crystal power substrate (ECPS) in a high-speed circuit package is proposed for suppressing the power/ground planes noise (P/GPN) and the corresponding electromagnetic interference (EMI). The ECPS is simply realized by periodically embedding the high dielectric-constant rods into the conventional package substrate between the continuous power and ground planes. With a small number of embedded rods and low rod filling ratio, the proposed ECPS design can efficiently eliminate the noise of 30dB in average within several designed stopbands. In addition, the radiation or EMI resulting from the P/GPN is also significantly reduced over 25dB in the stopbands. The excellent noise and EMI suppression performance for the proposed structure are verified both experimentally and numerically. Reasonably good consistency is seen.     

A novel power planes with low radiation and broadband suppression of ground bounce noise using photonic bandgap structures

A novel power/ground planes design for eliminating the ground bounce noise (GBN) in high-speed digital circuits is proposed by using low-period photonic bandgap (PBG) structure. Keeping solid for the ground plane and designing low-period PBG pattern on the power plane, the proposed structure omni-directionally behaves highly efficient suppression of GBN (over 50 dB) within broadband frequency range from 1 GHz to 4 GHz. Although the power plane has low-period perforation, the proposed structure still performs with relatively low radiation within the stopband compared with the solid power/ground planes. The low radiation and high suppression of the GBN for the proposed structure are checked both experimentally and numerically. Good consistency is seen.     

Study of the ground bounce caused by power plane resonances

We describe Delta-I noise caused by power plane resonances in multilayer boards. First, we study the effect of power plane resonances on the ground bounce of the system by performing finite-difference time-domain (FDTD) simulations. We simulate the voltage fluctuations at one point of the printed circuit board (PCB) due to a current surge between the power planes in a different point. Next, two methods to prevent this ground bounce effect are investigated. The first method consists of adding lumped capacitances to the design. The effect of one large capacitor is compared to the effect of adding a “wall” of smaller capacitors. A second approach is to isolate the chips by etching a slot around the sensitive integrated circuits (ICs) and connecting both sides by a small inductor. Both methods provide excellent protection against power plane resonances     

Estimation of ground bounce effects on CMOS circuits

Ground bounce estimation is important to determine the impact of simultaneous switching of input/output (I/O) drivers and clock drivers on the performance of application-specific integrated circuits (ASIC's). In this paper, we develop models to estimate the peak and damped resonance noise of the ground and power bounce. These models are developed for both long and short channel devices. Comparison with H-simulation program with integrated circuit emphasis (HSPICE) simulation indicates a good match. These models are simple and suitable for hand calculation     

A novel power plane with integrated simultaneous switching noise mitigation capability using high impedance surface

A novel technique for suppressing power plane resonance at microwave and radio frequencies is presented. The new concept consists of replacing one of the plates of a parallel power plane pair with a high impedance surface or electromagnetic band gap structure. The combination of this technique with a wall of RC pairs extends the lower edge of the effective bandwidth to dc, and allows resonant mode suppression up to the upper edge of the band-gap. The frequency range for noise mitigation is controlled by the geometry of the HIGP structure.     

Embedded power plane with ultra-wide stop-band for simultaneously switching noise on high-speed circuits

An embedded band selective (EBS) power plane is proposed using the hybrid-cell periodic structure. Because the periodic connections of the unit-hybrid-cell select different frequency rejection bands, the proposed EBS power plane performs ultra-wideband suppression of the simultaneously switching noise (about 9 GHz) with on average, over 60 dB noise elimination. This excellent behaviour is both numerically and experimentally validated.     

A speed, power, and supply noise evaluation of ECL driver circuits

We present an emitter coupled logic (ECL) active pull-down (APD) circuit which can provide a 10:1 ratio between active and inactive currents. The new APD circuit is compensated for variations in supply and temperature via a clamp voltage. The proposed circuit is evaluated by comparing its performance (in terms of speed, power dissipation, and generated supply noise) with the performance of five other driver circuits     

Composite effects of reflections and ground bounce for signal line through a split power plane

The signal propagating along a microstrip line over a slot on the power plane will suffer from composite effects of reflected noise by a discontinuity in signal return path and ground bounce between power and ground planes. A new equivalent circuit model is proposed and simulations are performed for multilayer structures to characterize these composite effects. An experimental setup is devised to demonstrate significant coupling between signal lines due to the slot-induced ground bounce. Favorable comparison between the simulation and measured results validates the proposed equivalent circuit model and analysis approach.     

电磁带隙结构在抑制电源层上噪声的应用

本文在阐述电磁带隙结构的基础上,从理论上分析其原理,结合印制电路板电源层存在的瓶颈,即目标阻抗随着设计频率的不断上升而变得越来越难控制。电磁带隙结构最早应用在天线结构中,而本文引用到PCB板电源完整性的设计中来达到抑制高频谐振的目的,并且通过Slwave建模仿真验证了其正确性。     

Achieving both wideband mitigation of ground bounce noise and good signal integrity by novel period structure

A double-square-ring slot period structure is proposed, designed in the power plane of the circuit board to suppress the ground bounce noise (GBN) in high-speed circuits. The novel design is based on the ring splits that connect the adjacent square patches in the power plane, which results in a wideband mitigation of the GBN ranging from 500 MHz to 5.5 GHz. The impact of the etched structures on the signal integrity (SI) is also investigated. Results show that good SI can be maintained while using the novel period structure in the power plane, and further improvement of the SI performance can be obtained by employing differential pairs of microstrip line for signals.     

A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits

Design of noise detector circuits as compact as standard logic cells is proposed. High-density large-scale digital integrated circuits that embed such built-in noise detectors enable in-depth characterization of dynamic power supply and ground noises. Dependence of power supply and ground voltage drops on the location of active cell rows within 1.8-V standard cell-based digital circuits are consistently measured by 1.8- and 2.5-V built-in detectors fabricated in a 0.18-/spl mu/m CMOS triple-well technology. Measurements also show that ground noise distribution is distinctively more localized than power supply counterparts due to the presence of a substrate.     

A novel defected ground structure for planar circuits

A new compact defected ground structure (DGS) is proposed for the microstrip line. The structure is compact in microstrip line direction. Here, this DGS is used to design a compact low pass filter (LPF) that is at least 26.3% more compact lengthwise than other reported compact structures and has sharper transition knee.     

含Zigzag有限地结构的新型手机倒L天线系统

在讨论手机有限接地板对倒L天线辐射及匹配性能影响基础上,结合倒L天线工作原理及手机结构的限制特征,提出了一款拥有Zigzag寄生结构的新型手机有限地。它与典型倒L天线结合,成功克服紧缩结构下天线辐射效率及匹配欠佳的问题;在GSM900频段处实现相对带宽达24%（VSWR〈2）,为普通单极天线的3倍左右,有效拓展了单极天线的工作带宽。     

Low power low noise high speed tunable CMOS radiation detection system

This paper presents a design of low power and low noise, high speed readout front-end system for semiconductor detectors. The architecture comprises a folded cascode charge sensitive amplifier with gain enhancement, a pole-zero cancellation circuit and a complex shaper circuit with Gm-C topology. A local feedback amplifier based on a wide swing gain boosting scheme with dc level shifting has been used. The system has been fabricated in a 0.13-µm CMOS technology with a single 1.2-V supply voltage. Experimental results show the flexibility of the system where the key parameters, such as decay time, charge gain and peaking time can be tuned. For a nominal peaking time of 150 ns the power consumption of the entire channel is less than 5 mW. A power consumption-low noise tradeoff will be considered to match a detector capacitance of 5 pF. The output pulse has a peak amplitude of 200 mV for a charge of 10 fC from the detector and achieves a linearity better than 1% up to an input charge range of 12 fC.     

Coupling between microstrip lines with finite width ground plane embedded in thin-film circuits

Three-dimensional (3-D) interconnects built upon multiple layers of polyimide are required for constructing 3-D circuits on CMOS (low resistivity) Si wafers, GaAs, and ceramic substrates. Thin-film microstrip lines (TFMS) with finite-width ground planes embedded in the polyimide are often used. However, the closely spaced TFMS fines are susceptible to high levels of coupling, which degrades the circuit performance. In this paper, finite-difference time domain (FDTD) analysis and experimental measurements are used to demonstrate that the ground planes must be connected by via holes to reduce coupling in both the forward and backward directions. Furthermore, it is shown that coupled microstrip lines establish a slotline type mode between the two ground planes and a dielectric waveguide type mode, and that the connected via holes recommended here eliminate these two modes.     

A novel high speed multitap bus structure

Reducing reflections, noise, and settling time on a bus through unique selections of node terminations, bus characteristic impedance, and bus construction allows dramatically higher operating speed. The new structure is described, the theory discussed, and results from fully operational physical and electrical implementations are presented     

Passive cancellation of common-mode noise in power electronic circuits

It is well known that common-mode (CM) conducted electromagnetic interference (EMI) is caused by the common-mode current flowing through the parasitic capacitance of transistors, diodes, and transformers to ground in the power circuit. Because of the potential for interference with other systems it is necessary to attenuate this noise. Ordinarily this is accomplished by using a magnetic choke across the input power lines, resulting in penalties to the overall size and cost of the completed system. In order to lessen the requirement for this magnetic choke, there has been a desire to introduce noise cancellation techniques to the area of EMI. This text introduces a method of canceling the common-mode EMI by using a compensating transformer winding and a capacitor. Compared with other cancellation techniques, it is much simpler and requires no additional transistors and gate-drive circuitry since it merely adds a small copper winding and a small capacitor. By using this technique the size of the EMI filter can be reduced, especially for applications requiring high currents. In this paper, the new method for passive noise cancellation is applied to many popular converter and inverter topologies. The method, results, and ramifications of this technique are presented in order of appearance.     

BiCMOS circuits for high speed current mode D/A converters

A new BiCMOS current cell and a BiCMOS current switch for high speed, self-calibrating, current-steering D/A converters are described. The BiCMOS current cell can be realized in a BiCMOS process or in a conventional CMOS process using a substrate PNP transistor, while the BiCMOS current switch is intended for implementation in a BiCMOS process. The performance of these circuits has been demonstrated in 0.8 μm BiCMOS and 1.2-μm CMOS technologies. A detailed noise analysis of the BiCMOS current cell indicates that noise during the calibration phase limits its relative accuracy to about 150 ppm. This is substantiated by measured results which show a relative matching of about 100-150 ppm, which is the equivalent of about 13 b performance. Measurement results also indicate that the absolute accuracy of the BiCMOS current cell is better than 0.5% over the designed current range, which is better than that of previously reported designs. Test results for the BiCMOS current switch indicate that a 10-90% switching time of 0.9 ns has been achieved. Furthermore, the switching time of the new BiCMOS switch is very insensitive to current level and input waveform compared to conventional CMOS switches. A 4-b D/A converter based on these components has been fabricated, and test results have demonstrated that it is functional. This DAC will be used as the internal DAC of a ΣΔ modulator for over-sampled video and digital radio applications