三维集成封装中的TSV互连工艺研究进展

为顺应摩尔定律的增长趋势,芯片技术已来到超越"摩尔定律"的三维集成时代。电子系统进一步小型化和性能提高,越来越需要使用三维集成方案,在此需求推动下,穿透硅通孔(TSV)互连技术应运而生,成为三维集成和晶圆级封装的关键技术之一。TSV集成与传统组装方式相比较,具有独特的优势,如减少互连长度、提高电性能并为异质集成提供了更宽的选择范围。三维集成技术可使诸如RF器件、存储器、逻辑器件和MEMS等难以兼容的多个系列元器件集成到一个系统里面。文章结合近两年的国外文献,总结了用于三维集成封装的TSV的互连技术和工艺,探讨了其未来发展方向。     

3D堆叠芯片硅通孔的电-热-力耦合构形设计

建立了3D堆叠芯片硅通孔(TSV)单元体模型,在单元体总体积和TSV体积占比给定时,考虑电-热-力耦合效应,以最高温度、(火积)耗散率、最大应力和最大形变为性能指标,对TSV横截面长宽比和单元体横截面长宽比进行双自由度构形设计优化.结果表明,存在最佳的TSV横截面长宽比使得单元体的最高温度、(火积)耗散率和最大应力取得极小值,但对应不同优化目标的最优构形各有不同,且TSV两端电压和芯片发热功率越大,其横截面长宽比对各性能指标的影响越大.铜、铝、钨3种材料中,钨填充TSV的热学和力学性能最优,但其电阻率较大.铜填充时,4个指标中最大应力最敏感,优先考虑最大应力最小化设计需求以确定TSV几何参数,可以较好兼顾其他性能指标.     

硅通孔尺寸与材料对热应力的影响

通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。     

3-D Structure Design and Reliability Analysis of Wafer Level Package With Stress Buffer Mechanism

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design     

3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems

Three-dimensional (3-D) hyperintegration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components to form highly integrated micro-nano systems. This 3-D hyperintegration is expected to lead to an industry paradigm shift due to its tremendous benefits. Worldwide academic and industrial research activities currently focus on technology innovations, simulation and design, and product prototypes. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of InfoTech-NanoTech-BioTech systems. This paper overviews the 3-D hyperintegration and packaging technologies, including motivations, key technology platforms, status, and perspectives towards commercialization. The challenges associated with the 3-D technologies are addressed, including integration architectures and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure.      

Optimization for Chip Stack in 3-D Packaging

We have been developing three-dimensional (3-D) packaging technology for forming through-type electrodes in chips that are then directly connected in stacks. The model examined in this study is defined by its simple structure. The structure was optimized for successful connection in a chip stack without degrading the features of the chips. The use of this structure enabled a stable and rigid connection, and a four-layer chip stack assembled on a ceramic substrate exhibited adequate thermal cycle performance. This paper discusses how the structure of terminals was optimized for chip stacking. A finished package assembled from static random access memory (SRAM) with through-type electrodes was confirmed to operate well and exhibit normal functioning.     

Fabrication and performance of a micromachined 3-D solenoid inductor

A high-Q and f_res (self-resonant frequency)solenoid inductor was fabricated by using the microelectromechanical systems(MEMS) technology with air-core structure. This inductor has an air core and an electroplated copper coil to reduce the series resistance, and the solenoid structure with laterally laid out structure saves the chip area significantly. The measurement results show that this inductor has high Q-factor and stable inductance over wide range of operating frequency. The maximum Q-factor of this inductor is 38 and the inductance is 1.78 nH at 5 GHz with an air core of 45 μm. Moreover, the Q-factor and the inductance grow with the increasing of the air core.     

用于微电子封装的电子胶粘剂及其涂覆工艺

介绍了电子胶粘剂及其涂覆工艺,其所涉及的工艺有大量式点胶(Mass Dispensing),接触式点胶(Contact Dispensing),非接触式点胶,总结了各种分配技术的优缺点,指出了不同分配技术的适用情况,提出电子胶粘剂涂覆工艺技术方案。     

硅微喷阵列芯片的设计、制作与应用研究

介绍了一种用于制作生物微阵列的新型微喷阵列芯片。基于半导体光刻技术和干法刻蚀技术,成功制作了喷孔外侧含有间隙环的硅微喷阵列芯片,解决了溶液进样难、微阵列样品点缺失、样品点漂移以及液体回流等问题。在5 kPa气压驱动下,该芯片中的样品能在3.4 mm×3.4 mm的玻璃片上制成5×5样品微阵列,25个点的直径平均值为356μm,直径的变异系数(25个点直径的标准偏差与算术平均值的比值)为2.8%。计算流体力学模拟结果和实验结果均表明,该微喷阵列芯片能快速、稳定地制作出样品点大小均一的微阵列,进一步推动了微阵列芯片的应用和发展。     

三维循序集成CMOSFET结构设计方法研究

详细介绍了三维集成的基本概念,针对二维SoC集成、三维并行TSV集成和三维循序集成的特点进行深入描述和比较.分析了三维循序集成CMOSFET结构的发展现状,包括早期的三维器件级集成设计、基于SOI的平面型CMOSFET三维循序集成设计,以及共包围栅SiNWFET三维循序集成设计.结合各种三维循序集成CMOSFET结构设计方法的特点,提出一种双层隔离三维循序集成SNWFET结构设计方法,为三维集成CMOSFET结构设计提供了一种新的解决方案.     

3-D MCM封装技术及其应用

介绍了超大规模集成电路（VLSI）用的3-D MCM封装技术的最新发展，重点介绍了3-D MCM封装垂直互连工艺，分析了3-D MCM封装技术的硅效率、复杂程度、热处理、互连密度、系统功率与速度等问题，并对3-D MCM封装的应用作了简要说明。     

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.     

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.     

三维微结构制作现状与进展

随着微机电系统(MEMS)的深入研究和快速发展,三维微细加工技术对于微机电的开发和生产具有非常重要的意义.详细介绍了现阶段三维微结构各种制作方法和工艺技术,分析了其原理和特点,比较了各种方法的优劣;讨论了三维微结构开发现状及有待解决的关键技术,综述了利用电子束曝光技术进行三维微结构制作的应用现状并指出了其发展前景.     

Low Thermal Budget Processing for Sequential 3-D IC Fabrication

Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. The authors demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 degC low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below     

Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in–package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 $mu{hbox {m}}$, lower flip chip interconnect height between the chip and the carrier down to 35 $mu{hbox {m}}$, 40–50- $mu{hbox {m}}$ low loop wire bonding on overhang by direct reverse wire bonding method using 1-mil-diameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.      

Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power

The existing 3-D thermal-via allocation methods are based on the steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering the temporally and spatially variant thermal-power. The transient temperature is calculated by macromodel with a one-time structured and parameterized model reduction, which also generates temperature sensitivity with respect to thermal-via density. The proposed thermal-via allocation minimizes the time-integral of temperature violation, and is solved by a sequential quadratic programming algorithm with use of sensitivities from the macromodel. Compared to the existing method using the steady-state thermal analysis, our method in experiments is 126$times$ faster to obtain temperature, and reduces the number of thermal vias by 2.04$times$ under the same temperature bound.      

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.      

Novel Bumping and Underfill Technologies for 3D IC Integration

In previous work, novel maskless bumping and no‐flow underfill technologies for three‐dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low‐volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no‐flow underfill material named “fluxing underfill” is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two‐tier stacked TSV chips are sucessfully stacked.     

用于3D封装的带TSV的超薄芯片新型制作方法

提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。