Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec     

Fluorine Passivation in Gate Stacks of Poly-Si/TaN/HfO2 (and HfSiON/HfO2)/Si Through Gate Ion Implantation

Fluorine passivation in poly-Si/TaN/HfO₂/p-Si and poly-Si/TaN/HfSiON/HfO₂/p-Si gate stacks with varying TaN thickness through gate ion implantation has been studied. It has been found that when TaN thickness was less than 15 nm, mobility and subthreshold swing improved significantly in HfO₂ nMOSFETs; while there was little performance improvement in HfSiON/HfO₂ nMOSFETs due to the blocking of F atoms by the HfSiON layer in gate dielectrics, as has been proved by the electron energy loss spectroscopy mapping     

Low-Frequency Noise Assessment of Silicon Passivated Ge pMOSFETs With TiN/TaN/ HfO2 Gate Stack

The low-frequency noise of pMOSFETs fabricated in epitaxial germanium-on-silicon substrates is studied. The gate stack consists of a TiN/TaN metal gate on top of a 1.3-nm equivalent oxide thickness HfO₂/SiO₂ gate dielectric bilayer. The latter is grown by chemical oxidation of a thin epitaxial silicon film deposited to passivate the germanium surface. It is shown that the spectrum is of the 1/f^gamma type, which obeys number fluctuations for intermediate gate voltage overdrives. A correlation between the low-field mobility and the oxide trap density derived from the 1/f noise magnitude and the interface trap density obtained from charge pumping is reported and explained by considering remote Coulomb scattering     

The Effect of an Yttrium Interlayer on a Ni Germanided Metal Gate Workfunction in SiO2/HfO2

In this letter, the tuning of a nickel fully germanided metal gate effective workfunction via a hyperthin yttrium (Y) interlayer at the bottom of the metal electrode was demonstrated on both SiO₂ and HfO₂. By varying the Y interlayer thickness from 0 to 9.6 nm, a full range of workfunction tuning from 5.11 to 3.65 eV has been achieved on NiGeY/SiO₂ stacks. It was also found that the chemical potential of the material that is adjacent to the gate electrode/gate insulator plays an important role in the determination of the effective workfunction. This work-function tuning window was observed to decrease to a range of 5.08-4.25 eV on NiGeY/HfO₂ stacks.     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

TiO_2/SiO_2和TiO_2/SiO_xN_y层叠结构高k栅介质比较研究

以射频磁控溅射为主要工艺,制备了TiO2/SiO2和TiO2/SiOxNy两种层叠结构栅介质。对C-V特性和漏电特性的测试表明,SiO2和SiOxNy等界面层的引入有效地降低了TiO2栅介质电荷密度及漏电流,而不同层叠结构的影响主要通过界面电学性能的差异体现出来。对漏电特性的进一步分析显示,TiO2/SiO2结构中的缺陷体分布和TiO2/SiOxNy结构中的缺陷界面分布是导致电学性能差异的主要原因。综合比较来看,TiO2/SiOxNy结构栅介质在提高MOS栅介质性能方面有更大的优势及更好的前景,有助于拓展TiO2薄膜在高k栅介质领域的应用。     

SiGe MOS器件SiO2栅介质低温制备技术研究

为了获得电学性能良好的SiGe PMOS SiO2栅介质薄膜，采用等离子增强化学汽相沉积（PECVD）工艺，对低温300℃下薄膜制备技术进行了研究。实验表明，采用适当高温、短时间对PECVD薄膜退火有助于降低薄膜中电荷密度和界面态密度。该技术用于SiGe PMOSdgrm,在300K常温和77K低温下，其跨导分别达到45mS/mm和92．5mS/mm(W/L=20μm/2μm).     

Yttrium- and Terbium-Based Interlayer on SiO2 and HfO2 Gate Dielectrics for Work Function Modulation of Nickel Fully Silicided Gate in nMOSFET

Novel yttrium- and terbium-based interlayers (Y_IL and Tb_IL, respectively) on SiO₂ and HfO₂ gate dielectrics were employed for NMOS work function Phi_m modulation of undoped nickel fully silicided (Ni-FUSI) gate. Bandedge Ni-FUSI gate Phi_m of ~4.11 and ~4.07 eV was obtained by insertion of ultrathin (~1 nm) Y_IL and Tb_IL, respectively, on the SiO₂ gate dielectric in a gate-first process (with 1000 degC anneal). NiSi Phi_m on SiO₂ could also be tuned between the Si midgap and the conduction bandedge E_C by varying the interlayer thickness. The achievement of NiSi Phi_m around 4.28 eV on the HfO₂ gate dielectric using interlayer insertion makes this an attractive Phi_m modulation technique for Ni-FUSI gates on SiO₂ and high-k dielectrics     

Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

Performance improvement of self-aligned HfO2/TaN and SiON/TaN nMOS transistors

Direct-etched HfO₂/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO₂/poly transistors. The performance enhancement requires a combination of EOT scaling and an appropriate interface layer control. The performance of the direct-etched TaN gated HfO₂ based transistors is also compared to the performance of similar TaN gated SiON based transistors. It is observed that for equal g_m the leakage is lower for HfO₂ based transistors, despite the lower EOT for the HfO₂ based devices.     

0.86-nm CET Gate Stacks With Epitaxial$hboxGd_2hboxO_3$High-$k$Dielectrics and FUSI NiSi Metal Electrodes

In this letter, ultrathin gadolinium oxide$(hboxGd_2hboxO_3)$high-$k$gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a$hboxGd_2hboxO_3$thickness of 3.1 nm yield a capacitance equivalent oxide thickness of$ CET = hbox0.86 hboxnm$. The extracted dielectric constant is$k = hbox13-hbox14$. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.     

TiO_2/SiO_2、ZrO_2/SiO_2多层介质膜光学损耗及激光损伤研究

以TiO_2/SiO_2及ZrO_2/SiO_2多层介质膜为例,测试了不同工艺条件及不同膜系结构下薄膜样品的光学损耗及激光损伤阈值,同时对实验结果作了初步的分析讨论.     

Effects of Al2O3 Dielectric Cap and Nitridation on Device Performance, Scalability, and Reliability for Advanced High- κ/Metal Gate pMOSFET Applications

A pFET threshold-voltage (Vt) reduction of about 200 mV is demonstrated by inserting a thin Al₂O₃ layer between the high-k dielectric and the TiN gate without noticeable degradation of other electrical properties. HfSiO_propcapped with 9 Aring of thin Al₂O₃obtains a low long-channel Vt of -0.37 V (the lowest among those with TiN gate), a high mobility of 59 cm² /V ldr s at 0.8 MV/cm (92% of universal value), a negligible equivalent- oxide-thickness (EOT) increase of 0.1 Aring (compared to the uncapped reference), and a low Vt instability of 4.8 mV at 7 MV/cm. It also passes the ten-year negative-bias-temperature-instability (NBTI) lifetime specification with a gate overdrive of -0.7 V. This indicates that thin Al₂O₃obtains caps are beneficial to the pFET applications. In contrast, nitrogen incorporation in the Al₂O₃-capped HfSiO_prop is not favorable because it increases the Vt by 50-140 mV, degrades the mobility by 10%-22%, increases the EOT by 0.5-0.8 Aring and the Vt instability by 5-13 mV, and reduces the NBTI lifetime by four to five orders of magnitude. Compared to postcap nitridation, high-k nitridation results in more severe degradation of these properties by incorporating nitrogen closer to the Si/SiO₂ interface.     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Interface characterization of silicon epitaxial lateral growth overexisting SiO2 for three-dimensional CMOS structures

The silicon-silicon dioxide interface created by the epitaxial lateral growth of monocrystalline silicon (ELO) over existing thermally oxidized silicon was investigated using a novel device structure. This structure is proposed as the basic building block of technology for the fabrication of locally restricted three-dimensional integrated CMOS circuits, as well as advanced bipolar devices. Results are reported from the investigation of the surface states of this silicon-on-insulator (SOI) interface. It is demonstrated that these interfaces can exhibit characteristics comparable to those interfaces created by the thermal oxidation of silicon. The SOI interface surface state densities, as grown, were measured to be about 2×10¹¹ cm^-2 eV^-1 at midgap energies. It is believed that H₂ from the epitaxial growth ambient is trapped at the interface and neutralizes surface states     

A Minimized SiO2 Waveguide With an Antiresonant Reflecting Structure for Large-Scale Optical Integrations

A minimized SiO₂ waveguide with an antiresonant reflecting buffer, a SiO₂ core, and an air cladding is presented. The buffer includes multiple periods of antiresonant reflecting structure to lower leakage loss to the substrate. Theoretically speaking, when there are three periods of etch-through antiresonant reflecting structures, one obtains a straight minimized SiO ₂ waveguide with a low leakage loss (<0.01 dB/cm) and a bending radius as small as 15 mum (because of the large index contrast between the core (SiO₂) and the air cladding in the lateral direction)     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO₂进行干法刻蚀, 研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系, 这为如何获得垂直的刻蚀侧壁提供了参考。     

氧化硅RIE刻蚀工艺研究

利用反应等离子刻蚀技术对SiO2进行干法刻蚀,研究了不同刻蚀条件对刻蚀速率、刻蚀选择比、刻蚀面粗糙度、刻蚀均匀性等的影响。分析得出了刻蚀侧壁角度与刻蚀选择比以及抗蚀掩模自身的侧壁角度之间存在的数学关系,这为如何获得垂直的刻蚀侧壁提供了参考。     

Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

MOSFETs incorporating ZrO₂ gate dielectrics were fabricated. The I_DS-V_DS, I_DS-V_GS , and gated diode characteristics were analyzed to investigate the ZrO₂/Si interface properties. The interface trap density (D _it) was determined to be about 7.4times10¹² cm ^-2middoteV^-1 using subthreshold swing measurement. The surface-recombination velocity (s₀) and the minority carrier lifetime in the field-induced depletion region (tau _0,FIJ) measured from the gated diodes were about 3.5times10 ³ cm/s and 2.6times10^-6 s, respectively. The effective capture cross section of surface state (sigma_s) was determined to be about 5.8times10^-16 cm² using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxides was also made