Spot-size converted 1.3 μm laser with butt-jointed selectivelygrown vertically tapered waveguide

A 1.3 μm laser has been developed with a butt-jointed selectively grown spot-sire converter (SSC). The SSC vertically tapered waveguide and strained multiquantum well (MQW) active region are independently optimised. The laser was buried with semi-insulating InP to reduce optical loss in the SSC. A threshold current of 7 mA and an output power of >20 mW were obtained. Minimum coupling loss to a flat-end fibre of 1.06 dB was achieved. Long-term stability was also confirmed     

Two-layer resist structure for electron-beam fabrication of a submicrometer gate length GaAs device

A two-layer resist structure using EBR-9 and PMMA for fabricating a fine metal line with a mushroom-like cross-sectional profile is reported. The structure provides T-shaped resist cavities with undercut profiles using electron-beam exposure. With the optimum developing condition, the bottom opening is as small as 0.1 µm, and the top opening is wide enough not to require an additional exposure in order to obtain a mushroom-like metal lift-off pattern. A Monte Carlo calculation is carried out in order to analyze the profile of the two-layer resist structure, and it is shown that an undercut T-shaped resist profile with a 0.1-µm bottom opening can be obtained using a high-sensitivity resist on a low-sensitivity resist structure. A 0.15-µn mushroom-like lift-off metal profile has been fabricated on a 0.1-µm recessed GaAs substrate by the use of this resist structure.     

Multiquantum-well lasers with tapered active stripe for direct coupling to single-mode fiber

We demonstrate narrow beam divergence in 1.3-/spl mu/m wavelength multiquantum-well (MQW) lasers with an active stripe horizontally tapered over the whole cavity, for direct coupling to single mode-fibers. The lasers have reduced output beam divergence in a simple structure which does not contain an additional spot-size transformer. The fabricated laser shows narrow beam divergence of /spl sim/12/spl deg/, while a low-threshold current of 6.9 mA and a high efficiency of 0.62 mW/mA are realized. Furthermore, a direct-coupling efficiency to a single-mode fiber is -4.0-dB and -3-dB alignment tolerance is /spl plusmn/2.5 /spl mu/m.     

Device design for the submicrometer p-channel FET with n+polysilicon gate

CMOS has become one of the most important technologies for VLSI applications. If the conventional n⁺polysilicon gate approach is to be maintained for VLSI CMOS, the p-channel transistor will cause problems in scaling down to submicrometers due to the counter-doping that is necessary to adjust the threshold voltage to a reasonable value. The depth of the p⁺source-drain junctions will also cause short-channel effects. This paper presents in-depth analysis of the submicrometer p-channel transistor structure. The effects of the counter-doping junction depth and the source-drain junction depth on the device subthreshold characteristics are discussed. Criteria for the submicrometer p-channel transistor structure with good subthreshold characteristics are presented. A new technique for minimizing the counter-doping junction depth is also presented. Submicrometer p-channel transistors with n⁺polysilicon gate were fabricated using this new technique as well as techniques for forming very shallow p⁺-junctions. Devices with submicrometer channel lengths showed very good subthreshold characteristics, as predicted by simulations.     

Insulated gate bipolar transistor with trench gate structure of accumulation channel

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simu-lation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm~2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K,respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.     

具有积累层沟道的槽栅IGBT结构

提出了一种具有积累层沟道的槽栅IGBT结构。仿真结果表明：在阻断电压为1200V,集电极电流密度为100 A/cm2,温度分别为300K和400K下的情况下,积累层沟道槽栅IGBT的正向压降分别为1.5V 和2V而常规槽栅IGBT分别为1.7V和2.4V。新结构比常规槽栅IGBT具有更低的开态压降和更大的正向安全工作区。文中同时分析了积累层沟道槽栅IGBT的阻断特性和关断特性。     

Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.     

Determination of effective saturation velocity in n+self-aligned GaAs MESFET's with submicrometer gate lengths

The dependence of effective saturation velocity on gate length in n⁺self-aligned GaAs MESFET's with submicrometer gate lengths has been determined by comparing experimentalI-Vcharacteristics with that obtained from one-dimensional analysis and two-dimensional simulation. The experimentalI-Vcharacteristics have been precisely matched to the theoretical ones calculated by two-dimensional simulation with a quasi-static (effective) velocity-electric-field relationship and reasonable doping profiles. The effective saturation velocity determined by best fit is 2.3 × 10⁷cm/s, and is independent of the gate length in 0.3- to 1.0-µm range. Though this high value gives evidence of the velocity overshoot effects, the constant characteristic disagrees with the expectation of the simulations based on nonstationary electron transport. On the contrary, the saturation velocity determined by using one-dimensional analysis decreases with an increase in the gate length. This dependence is explained by taking into account the channel pinchoff mechanism for drain current saturation before velocity saturation.     

Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.     

Analytical noise model with the influence of shot noise induced bythe gate leakage current for submicrometer gate-lengthhigh-electron-mobility transistors

A new high-frequency noise model which takes into account the influence of shot noise induced by the gate leakage current is introduced; the model accurately explains the observed minimum noise figure of submicrometer gate-length HEMT's as a function of frequency. Based on the steady-state Nyquist theorem for multiterminal devices recently reported, the minimum noise figure and the corresponding optimum source impedance of the microwave field effect transistors are expressed as functions of the measurable device parameters including noise spectral intensities and small-signal circuit parameters. The derived minimum noise figure can be shown to reduce to a simple form, i.e., an empirical relation with two fitting constant. The simple form and the derived formulas for the optimum source impedance can explain very well the experimental findings of the submicrometer gate-length high electron mobility transistors over the extended microwave frequency range and also provide the informations needed for the design of microwave low noise amplifiers     

A new LDD transistor with inverse-T gate structure

A new submicrometer inverse-T lightly doped drain (ITLDD) transistor structure for alleviating hot-electron effects is demonstrated. A thin extension of the polysilicon gate under the oxide sidewall spacer is formed, giving the gate cross section the appearance of an inverted letter T. Due to the unique self-aligned n+ T-to-gate feature facilitated by the conducting polysilicon extension, the "spacer-induced degradation" existing in a conventional LDD transistor is eliminated in ITLDD devices. This allows the use of low n- LDD doses for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicrometer ITLDD transistors with good transconductance and hot-electron reliability have been achieved. The new ITLDD transistor offers a promising device structure for future VLSI applications.     

Trench gate IGBT structure with floating P region

A new trench gate IGBT structure with a floating P region is proposed,which introduces a floating P region into the trench accumulation layer controlled IGBT(TAC-IGBT).The new structure maintains a low on-state voltage drop and large forward biased safe operating area(FBSOA)of the TAC-IGBT structure while reduces the leakage current and improves the breakdown voltage.In addition,it enlarges the short circuit safe operating area(SCSOA)of the TAC-IGBT,and is simple in fabrication and design.Simulation results indicate that,for IGBT structures with a breakdown voltage of 1200 V, the leakage current of the new trench gate IGBT structure is one order of magnitude lower than the TAC-IGBT structure and the breakdown voltage is 150 V higher than the TAC-IGBT.     

High breakdown GaN HEMT with overlapping gate structure

GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectric. The overlapping structure reduces the electric field at the drain-side gate edge, thus increasing the breakdown of the device. A record-high three-terminal breakdown figure of 570 V was achieved on a HEMT with a gate-drain spacing of 13 μm. The source-drain saturation current was 500 mA/mm and the extrinsic transconductance 150 mS/mm     

具有P型浮空区的槽栅IGBT结构

本文提出了一种具有P型浮空层的新型槽栅IGBT结构,它是在之前所提的一种积累层沟道控制的槽栅IGBT(TAC-IGBT)基础之上引入了一浮空P型层。此结构在维持原有TAC-IGBT低的正向导通压降和更大正向偏置安全工作区（FBSOA）的同时,减小了器件的泄漏电流,提高了器件的击穿电压,也使得器件的短路安全工作区大大提高,且制造简单,设计裕度增大。仿真结果表明：对于1200V的IGBT器件,具有P型浮空层的新型槽栅IGBT结构漏电比TAC-IGBT小近一个量级,击穿电压提高近150V。     

A deep submicrometer CMOS process compatible high-Q air-gap solenoid inductor with laterally laid structure

A high-quality (Q) on-chip solenoid inductor has been fabricated by 0.18 mm CMOS technology with air-gap structure. The solenoid structure with laterally laid out structure saves the chip area significantly and the air-gap suppresses the parasitic capacitances to obtain high-Q value. Additionally, with software ANSYS simulation, the solenoid inductor also possesses a higher strength for impact (80 000 times) in comparison to a spiral inductor. The measured peak-Q and peak-Q frequency with an air-gap are 8.8 and 1.7 GHz, respectively, which present almost 9% improvements in the magnitude and 54% in the peak-Q frequency in comparison to the conventional solenoid inductor at 8.1 and 1.1 GHz.     

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive V_TH shift within 0.4 V and negative V_TH shift within-1.2 V and it is robust and promising for high-resolution display.     

A sub-half-micron gate-length GaAs MESFET with new gate structure

New gate structure and fabrication technique for GaAs MESFET's have been developed. Utilizing the gate structure, sub-half-micron gate length can easily be obtained by conventional projection photolithography without any gate resistance increase and mechanical adhesion strength decrease.     

A novel GaAs FET with double camel-like gate structure

Extremely high potential barrier height and gate turn-on voltage of a novel GaAs field-effect transistor with n/sup +//p/sup +//n/sup +//p/sup +//n double camel-like gate structure are demonstrated. The maximum electric field and potential barrier height of the double camel-like gate are substantially enhanced by the addition of another n/sup +//p/sup +/ layers in gate region, as compared with the conventional n/sup +//p/sup +//n single camel-like gate. For a 1/spl times/100 /spl mu/m/sup 2/ device, a potential barrier height up to 2.741 V is obtained. Experimentally, a high gate turn-on voltage up to +4.9 V is achieved because two reverse-biased junctions of the double camel-like gate absorb part of positive gate voltage. In addition, the transistor action shows a maximum saturation current of 730 mA/mm and an extrinsic transconductance of 166 mS/mm.     

Unstable horizontal transverse modes and their stabilization with a new stripe structure

Kinks in the light output and other anomalous characteristics in stripe-geometry lasers were studied. It was found that these anomalies were caused by unstable horizontal, parallel to the junction, transverse modes. Introduction of a refractive-index guiding by Zn-diffusion stabilized the horizontal mode and removed the kink and other anomalies completely.     

A new structure GaAs MESFET with a selectively recessed gate

A new structure for GaAs MESFET's has been proposed. The structure features a gate recess which is formed on the original surface of an MBE grown GaAs active layer through selective etching of the overgrownn^{+}-Ga_{1- x}Al_{x}Assource/drain layer. Because of heavy doping in theGa_{1-x}Al_{x}Aslayer, the new MESFET structure offers a low source resistance. The selective etching technique for gate recess formation holds the MBE grown active layer thickness unchanged. As a result, the FET characteristics such as IDSSand Vpof devices fabricated from one wafer are strikingly uniform.