Low-voltage fully differential switched-current filters

An accurate high-frequency switched-current integrator based on low-voltage fully-differential folded-cascode current copiers is presented. A five-pole lowpass ladder filter has been integrated using a 1.2 μm n-well CMOS process without floating precision linear capacitors. Experimental results show an accurate filter response for sampling frequencies up to 5 MHz. Using a nominal 3.3 V power supply, the measured dynamic range is 66 dB and the power dissipation is 10 mW/pole     

Low-voltage micropower super class AB CMOS OTA

Novel class AB OTA topologies result from the combined use of local common-mode feedback and class AB input stages. They can operate at low supply voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results of a 0.5 /spl mu/m CMOS prototype show slew rate and unity-gain bandwidth enhancement factors of 180 and 4.5, respectively, compared to a conventional one-stage OTA.     

Low-voltage class AB buffers with quiescent current control

This paper presents a simple class AB buffer which is suitable for low-voltage (1.5 V) applications. The proposed buffer uses an adaptive load to reduce the sensitivity of the quiescent current to the process variation. The main feature of this scheme is its simplicity. The circuit was fabricated in a 2.0 μm digital CMOS process. Experimental results demonstrate that the buffer can operate with a supply voltage below 2 V, and it has the capability to drive small resistive loads     

Low-voltage bulk-driven class AB four quadrant CMOS current multiplier

In this paper a low voltage bulk-driven class AB four quadrant current multiplier is proposed. For the proposed multiplier a bulk-driven class AB current mode cell has been developed and the drain current equations for NMOS and PMOS transistors of the proposed cell have been derived. This cell is used as a basic building block for bulk-driven low voltage current squarer and copier circuit, which is finally used as the fundamental building block of the proposed low-voltage bulk-driven current multiplier operating at ±1 V. All the circuits are simulated using SPICE for 0.25 μm CMOS technology.     

High current class AB convertor technique

A high current class AB convertor technique offering both v.c.c.s. and c.c.c.s. capability is described. A simple realisation is proposed which provides peak output currents greater than 100 mA with low distortion and reduced supply drain over a useful frequency range.     

Low-voltage 32 Msample/s parallel pipelined switched-current ADC

A parallel switched-current A/D converter is presented. Eight time-interleaved switched-current ADCs operating at 4 Msample/s are used to increase the sampling rate. With channel compensation, the measured SFDR is >50 dB at 32 Msample/s with f_m=1.13 MHz. The performance of this experimental design is limited by noise and a fixed-pattern timing error that is not removed by the compensation algorithm     

Low-voltage, 10 bit switched-current ADC with 20 MHz inputbandwidth

Fully-differential first-generation switched-current memory cells with common-mode feedforward were used to implement a 1.5 bit/stage pipelined A/D converter in a standard digital CMOS process. The peak effective number of bits (ENOB) for input frequencies over 1 MHz is 7.43, and with a 20 MHz input signal sampled at 3 M sample/s, the measured SFDR and SNDR are 45.1 and 40.8 dB, respectively     

Low-voltage dynamic biasing technique for CMOS class ABcurrent-mode circuits

A novel dynamic biasing technique that can be used for the design of CMOS class AB current-mode circuits is presented. The approach takes advantage of the switched capacitor (SC) technique and enables extremely low voltage operations. An application of the proposed technique to the design of a basic input stage is given and simulations showing good agreement with the expected results are provided     

Marr小波变换的模拟开关电流技术实现

本文提出了用开关电流技术实现Marr小波变换的一种简单有效的方法,充分利用数学领域中功能强大的泰勒定理在频域中逼近Marr小波,并利用开关电流技术系统化模块化的优势从电路级上实现逼近的数学模型.文章通过尺度为1的Marr小波的设计仿真过程验证了这种设计方法的正确性.     

Power-efficient class AB CMOS buffer

A novel class AB unity gain voltage buffer is proposed. It is based on the use of quasi-floating gate (QFG) techniques in a super source follower topology. The circuit achieves dynamic current boosting with accurate control of quiescent currents and without penalty in supply voltage requirements or quiescent power consumption. Measurement results of the circuit, fabricated in a 0.5 mm CMOS technology, show a slew-rate enhancement by a factor 18.5 against the conventional super source follower, for the same bias current and supply voltage.     

Low-output-impedance class AB bipolar voltage buffer

A new ±1.5 V class AB bipolar voltage buffer that can drive low load impedance is presented. A current compensation technique is used for achieving a low output impedance, resulting in a large unitary gain bandwidth and low distortion. Simulation results are included demonstrating the circuit performance     

Low-power class AB current memory cell

A new class AB current memory circuit is presented that is suitable for low-power and low-voltage applications. The circuit applies simple feedback circuitry to adjust the quiescent current of the memory cell     

Compact class AB CMOS current mirror

Current mirrors are, together with differential pairs, the most common analogue building blocks in modern analogue and mixed-signal integrated circuits. Desirable features of current mirrors include: low standby power dissipation, wide input and output current swings, low supply voltage requirements, accurate current copy, and high linearity. Conventional class A topologies are unable to achieve simultaneously low quiescent power consumption and wide current swings, since they have maximum input and output currents limited by the DC bias currents. To overcome this shortcoming, class AB current mirrors have been proposed, which feature maximum currents not limited by the quiescent currents and reduced sensitivity to process tolerances [1]. Unfortunately, the additional circuitry required to achieve class AB operation often increases supply voltage requirements. For instance, the most common approach to achieve a class AB CMOS current mirror requires stacking of two MOS gate?source voltages [2]. This additional circuitry also often increases standby power consumption and adds extra intrinsic capacitances at the internal nodes. Another common issue is that quiescent currents are often dependent on supply voltage, process variations or temperature [2]. Other approaches are based on SC dynamic biasing [3], requiring the generation of two non-overlapping clock signals and suffering from charge injection errors.     

Monolithic class AB operational mirrored amplifier

A monolithic class AB operational amplifier with an extra output which supplies the difference between the mirrored supply currents is described. Such an operational mirrored amplifier (OMA) is a universal electronic building block particularly suited to the realisation of controlled current sources. The device, which contains a simulated p-n-p current mirror, has a bandwidth of 12 MHz and can supply a maximum output current of 20 mA.     

New switched-current integrator

A switched-current integrator configuration with greatly improved insensitivity to transistor mismatch is described. A universal integrator configuration is developed which performs an algorithm identical to the well known switched-capacitor universal integrator. This permits signal flowgraph synthesis of switched-current filters with similar properties to those of their switched-capacitor counterparts.<>     

Rail-to-rail super class AB CMOS operational amplifiers

Novel class AB single-stage operational amplifiers are presented. They feature rail-to-rail operation owing to the use of floating-gate input transistors. Initial charge of the floating gates is removed during fabrication, without any post-processing. The amplifiers are fast, simple, and able to operate at low supply voltages. They are highly power efficient owing to the enhanced (super) class AB operation based on adaptive biasing and local common-mode feedback. A 0.5 /spl mu/m CMOS implementation shows rail-to-rail operation with slew rates of about 40 V//spl mu/s for a load of 80 pF and 144 /spl mu/W of quiescent power consumption.     

An integrated low-voltage class AB CMOS OTA

We present a new circuit topology for a low-voltage class AB amplifier. The circuit shows superior current efficiency in the use of the supply current to charge and discharge the output load. It uses negative feedback rather than component matching to optimize current efficiency and performance, resulting in a current boost ratio exactly equal to one. Measurement results for an example circuit fabricated in a 2-μm CMOS process are given. The circuit uses a quiescent supply current of 0.2 μA and is able to settle to a 1% error in 1.1 ms for a 0.4-V input step and a load capacitance of 35 pF. The circuit design is straightforward and modular, and the core circuit can be used to replace the differential pair of other op-amp topologies     

A wide-band class AB monolithic power amplifier

A class AB Si monolithic power amplifier which achieves DC to 830-MHz small-signal bandwidth and delivers +20 dBm at 1-dB gain compression power and 100 MHz to a 50-Ω load is described. The circuits dissipates 540-mW quiescent power from a 12-V supply and has input and output impedances matched to 50 Ω. The circuit has a small die size, is housed in an inexpensive package, and exhibits excellent tolerance to input overdrive     

S/sup 2/I: a switched-current technique for high performance

A new switched-current memory cell is presented which enhances basic cell performance through successive refinement of the memorised sample. This is achieved in a two-step technique, called S/sup 2/I, in which the input sample is coarsely memorised, a process which introduces a combination of all the normal errors followed by detection and suppression of the combined errors. The circuit solution requires the addition to the basic memory cell of only extra switches and so carries few of the penalties associated with alternative techniques.<>     

Bulk-driven class AB fully-balanced differential difference amplifier

This paper presents a new low-voltage class AB fully-balanced differential difference amplifier (FB-DDA) employing the bulk-driven technique. At the FB-DDA differential pairs the bulk terminal of the MOS transistors are used as signal inputs in order to increase the common-mode input range under low supply voltage. At the class AB output stages the bulk terminal of the MOS transistors are used as control inputs in order to adjust the quiescent currents and compensate them against the process and temperatures (P/T) variation. The voltage supply of the FB-DDA is 0.7 V and the quiescent power consumption is 8.3 µW. The open loop voltage gain is 68 dB and the gain–bandwidth product is 168 kHz for 10 pF capacitive load. The circuit performance was simulated in Cadence/Spectre environment using the TSMC 0.18 µm CMOS process.