Induction machine fault detection using SOM-based RBF neural networks

A radial-basis-function (RBF) neural-network-based fault detection system is developed for performing induction machine fault detection and analysis. Four feature vectors are extracted from power spectra of machine vibration signals. The extracted features are inputs of an RBF-type neural network for fault identification and classification. The optimal network architecture of the RBF network is determined automatically by our proposed cell-splitting grid algorithm. This facilitates the conventional laborious trial-and-error procedure in establishing an optimal architecture. In this paper, the proposed RBF machine fault diagnostic system has been intensively tested with unbalanced electrical faults and mechanical faults operating at different rotating speeds. The proposed system is not only able to detect electrical and mechanical faults, but the system is also able to estimate the extent of faults.     

基于改进动态主元分析在半实物仿真系统中的研究

为了实现数据驱动技术在工业中的实际应用,开发了以蒸馏塔作为被控对象的半实物仿真系统,将数据驱动方法应用到流程工业半实物仿真系统.针对动态主元分析方法存在的计算负荷大,计算效率低的问题,提出了一种改进动态主元分析方法,利用不可区分度和交叉程度去除众多变量中的不相关变量或相关度较小的变量,减少数据量.针对系统中的典型故障,数据驱动方法能够检测出半实物仿真系统中的异常,而且与传统动态主元分析比较,改进算法降低漏报率和误报率,提高诊断可靠性,并且能及时检测出生产过程的微小故障.     

An Effective Neural Approach for the Automatic Location of Stator Interturn Faults in Induction Motor

This paper presents a neural approach to detect and locate automatically an interturn short-circuit fault in the stator windings of the induction machine. The fault detection and location are achieved by a feedforward multilayer-perceptron neural network (NN) trained by back propagation. The location process is based on monitoring the three-phase shifts between the line current and the phase voltage of the machine. The required data for training and testing the NN are experimentally generated from a three-phase induction motor with different interturn short-circuit faults. Simulation, as well as experimental, results are presented in this paper to demonstrate the effectiveness of the used method.      

Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style     

Fault location in multi-modular redundant systems

This paper describes a systematic design of a general m-order fault location network to detect and locate all possible subcritical faults in a multi-modular redundant system using decision elements. The fault distribution pattern propagating through various levels of the fault location network of a multi-modular redundant system is presented. The conditions for fault detection and location are also developed.     

A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification

A new neural network-based fault classification strategy for hard multiple faults in analog circuits is proposed. The magnitude of the harmonics of the Fourier components of the circuit response at different test nodes due to a sinusoidal input signal are first measured or simulated. A selection criterion for determining the best components that describe the circuit behaviour under fault-free (nominal) and fault situations is presented. An algorithm that estimates the overlap between different faults in the measurement space is also introduced. The learning vector quantization neural network is then effectively trained to classify circuit faults. Performance measures reveal very high classification accuracy in both training and testing stages. Two different examples, which demonstrate the proposed strategy, are described.     

Model-based fault diagnosis in electric drives using machine learning

Electric motor and power electronics-based inverter are the major components in industrial and automotive electric drives. In this paper, we present a model-based fault diagnostics system developed using a machine learning technology for detecting and locating multiple classes of faults in an electric drive. Power electronics inverter can be considered to be the weakest link in such a system from hardware failure point of view; hence, this work is focused on detecting faults and finding which switches in the inverter cause the faults. A simulation model has been developed based on the theoretical foundations of electric drives to simulate the normal condition, all single-switch and post-short-circuit faults. A machine learning algorithm has been developed to automatically select a set of representative operating points in the (torque, speed) domain, which in turn is sent to the simulated electric drive model to generate signals for the training of a diagnostic neural network, fault diagnostic neural network (FDNN). We validated the capability of the FDNN on data generated by an experimental bench setup. Our research demonstrates that with a robust machine learning approach, a diagnostic system can be trained based on a simulated electric drive model, which can lead to a correct classification of faults over a wide operating domain.     

Characterization, testing and reconfiguration of faults in mesh networks

Achieving fault-tolerance through incorporation of redundancy and reconfiguration is quite common. The distribution of faults can have several impacts on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire VLSI system unusable regardless of its component redundancy and its reconfiguration capabilities. Such fault patterns are called catastrophic fault patterns (CFPs). In this paper, we characterize catastrophic fault patterns in mesh networks when the links are bidirectional or unidirectional. We determine the minimum number of faults required for a fault pattern to be catastrophic. We consider the problem of testing whether a fault pattern is catastrophic. When a fault pattern is not catastrophic we study the problem of finding optimal reconfiguration strategies, where optimality is with respect to either the number of processing elements in the reconfigured network (the reconfiguration is optimal if such a number is maximized) or the number of bypass links to activate in order to reconfigure the array (the reconfiguration is optimal if such a number is minimized). The problem of finding a reconfiguration strategy that is optimal with respect to the size of the reconfigured network is NP-complete, when the links are bidirectional, while it can be solved in polynomial time, when the links are unidirectional. Considering optimality with respect to the number of bypass links to activate, we provide algorithms which efficiently find an optimal reconfiguration.     

基于集员未知输入观测器的风力机桨距执行器故障诊断

风力机一般放置在恶劣的环境中,其桨距执行器极易出现故障。文中针对一类含有未知但有界干扰和噪声的风力机系统的桨距执行器故障问题,设计了集员未知输入观测器对桨距的执行器故障进行检测并分离。采用气动机理和现代辨识原理建立风力机系统模型,通过优化未知输入观测器设计对系统中的干扰解耦,基于中心对称多胞体估计不考虑故障时残差的区间包络,并将其作为残差估计的上下动态阈值,实现状态估计。在上述基础上提出了利用一组集员未知输入观测器进行故障诊断的策略。仿真结果表明,在实验过程中,文中所设计的集员未知输入观测器准确地诊断出了风力机桨距执行器的3阶和5阶线性系统在发生突变故障和缓慢时变故障的时间和位置,证明了所提故障诊断策略的有效性。     

Intelligent fault diagnosis system of induction motor based on transient current signal

This paper presents a method for induction motor fault diagnosis based on transient signal using component analysis and support vector machine (SVM). The start-up transient current signal is selected as features source for fault diagnosis. Preprocessing of transient current signal is performed using smoothing and discrete wavelet transform to highlight the salient features of faults. In this work, independent component analysis, principal component analysis and their kernel are performed to reduce the dimension of features and to extract the optimal features for classification process. In this work, the influence of the number of component analysis towards diagnosis accuracy is also studied. SVM multi-class classification using one against all strategy is selected for classification tool due to good generalization properties. Performance of the system is validated by applying the system to induction motor faults diagnosis. According to the result, the system has potential to serve an intelligent fault diagnosis system in real application.     

Hybrid fault diagnosis for telerobotics system

Fault detection and isolation (FDI) of a class of networked control systems (NCS), applied for telerobotics system is studied in this paper. The considered NCS application is related to telerobotics system, where it is modelled with a hybrid manner, by including the continuous, discrete, uncertain, and stochastic aspects of all the system components. The main considered components of the NCS namely the network system and controlled system are completely decoupled according to their operation characteristics. The network part is taken as a discrete and stochastic system in presence of non-structured uncertainties and external faults, while the controlled part is considered as a continuous system in presence of input and output faults. Two model based fault diagnosis approaches are proposed in this paper. The first concerns a discrete and stochastic observer applied to the network system in order to detect and isolate system faults in presence of induced delay on the network part. The second is based on the analytical redundancy relations (ARR) allows detecting and isolating the input and output system’ faults. Experimental results applied on telerobotics system, show the performance and the limit of the proposed fault diagnosis approach.     

一种新的缩短随机测试序列长度的方法

本文提出了一种新的缩短随机测试序列长度的方法,它是在找到电路中难测故障分布的基础上,通过对电路的初始输入施加概率不等的“１”信号,使这些难测故障的测试率升至最大值,这样,就可以达到提高故障覆盖率和缩短测试序列长度的目的。     

基于神经网络的单通道冗余VLSI/WSI阵列重构算法

本文提出了一个基于Hopfield网络的单通道冗余VLSI/WSI阵列重构算法,根据阵列中缺陷单元的分布情况,构造相应的矛盾图模型,将阵列的重构问题转化为求矛盾图的独立集且使得独立集的顶点数恰为缺陷单元的个数,有效地解决了阵列的重构问题.实验结果表明,与传统的启发式方法相比,基于本文所提出的图论模型而采用的神经网络方法是一种简单、快速、高效的算法.     

Selection of Input Stimulus for Fault Diagnosis of Analog Circuits Using ARMA Model

The paper addresses the problem of fault diagnosis of analog circuits based on dictionary approach. The proposed approach first identifies an adequate set of test frequencies to optimize the process of detection and isolation of simulated fault scenarios. The circuit under test (CUT) is then excited by an input stimulus composed of a set of sinusoidal waveforms with the selected test frequencies. The circuit response, at different fault scenarios, is preprocessed by an autoregressive moving average (ARMA) model to yield a set of features formulating the fault dictionary. Collected features are utilized to train and test a back-propagation (BP) neural network (NN) based classifier. Demonstrative results from soft fault simulation of two active circuit examples prove the excellent effectiveness of the proposed algorithm.     

Electrical steering of vehicles - fault-tolerant analysis and design

The topic of this paper is systems that need be designed such that no single fault can cause failure at the overall level. A methodology is presented for analysis and design of fault-tolerant architectures, where diagnosis and autonomous reconfiguration can replace high cost triple redundancy solutions and still meet strict requirements to functional safety. The paper applies graph-based analysis of functional system structure to find a novel fault-tolerant architecture for an electrical steering where a dedicated AC-motor design and cheap voltage measurements ensure ability to detect all relevant faults. The paper shows how active control reconfiguration can accommodate all critical faults and the fault-tolerant abilities are demonstrated on a warehouse truck hardware.     

配电网故障快速恢复方法

针对快速实现配电网故障恢复的问题,对智能配电网的故障、网络重构及故障恢复进行了分析。通过建立包含约束条件的配电网故障快速恢复数学模型,对网络拓扑搜索进行了研究。利用网络拓扑搜索与故障信息矩阵相结合的方法,解决了配电网故障定位问题。并就常见的35 kV永久配电故障,给出了35 kV电源故障快速恢复方案,针对解决方法进行了实际案例分析,验证了所提出方案的可靠性及有效性。     

基于神经网络与证据理论的模拟电路故障诊断

论述了利用多类电量测试信息、应用神经网络与D-S证据理论实现模拟电路故障诊断的基本原理,提出了一种基于可测点电压与不同测试频率下的电路增益经决策层信息融合的故障诊断新方法.分别利用此两类测试信息,各用一个独立的改进BP网络对电路进行初步诊断,再运用所提融合诊断算法实现故障定位.模拟实验结果表明:所提方法对硬故障与元件参数偏移较小的软故障均适用,故障定位准确率高.     

Fault Tolerant Control for a Class of Nonlinear Systems with Application to Near Space Vehicle

In this paper, a fault tolerant control (FTC) scheme, which is based on backstepping and neural network (NN) methodology, is proposed for a general class of nonlinear systems with known structure and unknown faults. Firstly, the linearly parameterized radial basis function (RBF) NNs are employed to approximate unknown system faults, and the network weights are adapted using adaptive on-line parameter-learning algorithms. Then an adaptive backstepping based FTC is designed to compensate for the effect of system faults. The asymptotical stability of the closed-loop system and uniform boundedness of the state tracking errors are proved according to Lyapunov theory. Finally, the designed strategy is applied to near space vehicle (NSV) attitude dynamics, and simulation results are presented to demonstrate the effectiveness of the proposed approach.     

Testing of Synchronizers in Asynchronous FIFO

This paper presents a test method for testing two-D-flip-flop synchronizers in an asynchronous first-in-first-out (FIFO) interface. A faulty synchronizer can have different fault behaviors depending on the input application time, the fault location, the fault mechanism, and the applied clock frequency. The proposed test method can apply the input patterns at different time and generate capture clock signals with different frequency regardless of phase-locked loop (PLL) of the design. To implement the proposed test method, channel delay compensator, delayed scan enable signal generator, launch clock generator, and capture clock generator are designed. In addition, a well-designed calibration method is proposed to calibrate all programmable delay elements used in the test circuits. The proposed test method evolves to several test sections to detect all possible faults of the two-D-flip-flop synchronizers in the asynchronous FIFO interface.     

Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors

A neural-network based analog fault diagnostic system is developed for nonlinear circuits. This system uses wavelet and Fourier transforms, normalization and principal component analysis as preprocessors to extract an optimal number of features from the circuit node voltages. These features are then used to train a neural network to diagnose soft and hard faulty components in nonlinear circuits. Our neural network architecture has as many outputs as there are fault classes where these outputs estimate the probabilities that input features belong to different fault classes. Application of this system to two sample circuits using SPICE simulations shows its capability to correctly classify soft and hard faulty components in 95% of the test data. The accuracy of our proposed system on test data to diagnose a circuit as faulty or fault-free, without identifying the fault classes, is 99%. Because of poor diagnostic accuracy of backpropagation neural networks reported in the literature (Yu et al., Electron. Lett., Vol. 30, 1994), it has been suggested that such an architecture is not suitable for analog fault diagnosis (Yang et al., IEEE Trans. on CAD, Vol. 19, 2000). The results of the work presented here clearly do not support this claim and indicate this architecture can provide a robust fault diagnostic system.