A silicon integrated opto-electro-mechanical displacement sensor

This paper describes a compact and low cost micro-opto-electro-mechanical displacement sensor. Our purpose is the fabrication of a long range, nanometer resolved encoder using a standard CMOS technology, in order to integrate the optical metrology system (photodiodes, analog and digital circuits) on a single chip. We introduce the interferometric linear encoder principle using diffraction gratings; then we present results of optical and electrical characterization of an optoASIC including photodiodes and associated electronic integrated on a standard 0.6 μm CMOS process. This CMOS circuitry is then included inside of a prototype of linear displacement encoder using the principle of diffraction gratings in reflection. Finally, we present the fabrication of micrometer and sub-micrometer diffraction gratings etched in silicon material, in order to obtain a higher encoder integration.     

100‐MHz CMOS circuits directly fabricated on plastic using sequential laterally solidified silicon

Abstract— CMOS TFT circuits were fabricated on plastic using sequential laterally solidified silicon combined with a low‐temperature CMOS process. The unity‐gain frequencies of the best of NMOS TFTs are greater than 250 MHz, and the CMOS ring oscillators operate at 100 MHz. To the best of the authors' knowledge, these are the highest‐frequency circuits ever fabricated directly on plastic. This high‐performance CMOS‐on‐plastic process can be applied to the fabrication of AMLCD integrated drivers and AMOLED pixels on plastic substrates.     

A CMOS-MEMS mirror with curled-hinge comb drives

A micromirror achieves up to /spl plusmn/4.7/spl deg/ angular displacement with 18 Vdc by a comb-drive design that uses vertical angled offset of the comb fingers. Structures are made from a combination of CMOS interconnect layers and a thick underlying silicon layer. Electrical isolation of the silicon fingers is realized with a slight silicon undercut etch, which disconnects sufficiently narrow pieces of silicon under the CMOS microstructures. The 1 mm by 1 mm micromirror is made of an approximately 40 /spl mu/m-thick single-crystal silicon plate coated with aluminum from the CMOS interconnect stack. The mirror has a peak-to-peak curling of 0.5 /spl mu/m. Fabrication starts with a conventional CMOS process followed by dry-etch micromachining steps. There is no need for wafer bonding and accurate front-to-backside alignment. Such capability has potential applications in biomedical imaging, optical switches, optical scanners, interferometric systems, and vibratory gyroscopes.     

Post-CMOS processing for high-aspect-ratio integrated siliconmicrostructures

Presents a new fabrication sequence for integrated-silicon microstructures designed and manufactured in a conventional complementary metal-oxide-semiconductor (CMOS) process. The sequence employs a post-CMOS deep silicon backside etch, which allows fabrication of high aspect ratio (25:1) and flat (greater than 10 mm radius of curvature) MEMS devices with integrated circuitry. A comb-drive resonator, a cantilever beam array and a z-axis accelerometer were fabricated using this process sequence. Electrical isolation of single-crystal silicon was realized by using the undercut of the reactive ion etch (RIE) process. Measured out-of-plane curling across a 120-μm-wide 25-μm-thick silicon released plate was 0.15 μm, which is about ten times smaller than curl of the identical design as a thin-film CMOS microstructure. The z-axis DRIE accelerometer structure is 0.4 mm by 0.5 mm in size and has a 25-μm-thick single-crystal silicon proof mass. The measured noise floor is 1 mG/√Hz, limited by electronic noise. A vertical electrostatic spring "hardening" effect was theoretically predicted and experimentally verified     

Actively recharged single photon counting avalanche photodiode integrated in an industrial CMOS process

An actively recharged single photon counting avalanche photodiode (SPAD) is integrated in a conventional CMOS process. A fast recharge through a low impedance path leads to a dead time lower than 10 ns. This outstanding feature allows one to work with pulse repetition rate up to 100 MHz in time correlated single photon counting based experiments. Biased 2.5 V above its breakdown voltage, the 30 μm² sensitive area photodiode has a maximum detection probability of about 20% at λ=440 nm and up to 5% in the visible part of the spectrum. At this bias condition, the dark count rate is as low as 60 Hz at room temperature, making a cooling of the microsystem unnecessary. The AR-SPAD exhibits no afterpulsing phenomenon revealing the maturity of the CMOS process used. The timing resolution of the AR-SPAD is less than 50 ps. For applications where the photons can be focused on the detector with an objective, the AR-SPAD is highly competitive with commercially available single photon counter. Furthermore, CMOS integration opens the way to arrays fabrication as well as co-integration of additional functions to develop smart optical sensors.     

Characterization of miniaturized one-side-electrode-type fluid-based inclinometer

In this study, electrical double-layer theory is applied to realize a one-side-electrode-type fluid-based inclinometer combined with complementary metal oxide semiconductor (CMOS) circuitry. Substrate penetration lithography was applied in the fabrication of high-aspect-ratio SU-8 container molds, and molds with heights 1.0 mm were fabricated. Polydimethylsiloxane (PDMS) was used as the container material, and electrodes were fabricated on a ceramic substrate. Considering the electrical double-layer property, low surface tension, the dielectric constant and the problem of volatilization, methanol and propylene carbonate were tested as electrolytes. A charge-balanced capacitance–voltage (C–V) conversion circuit was designed as a detection circuit for this sensor and it was fabricated using 0.35 μm CMOS technology. The sensor part and detection circuit were integrated in one ceramic packaging for realize a miniaturization of inclination sensor system. To overcome the surface tension of the PDMS surface, silicone oil was injected in the container to cover the entire inner surface so that the movement of solution in the container became smooth. The linearity of the analog output of ±60° inclination for container dimensions of Ø 4.0 mm × 1.0 mm (diameter × thickness) was less than 6%/F.S. The minimum moving angle and response time were 0.4° and 0.9 s, respectively, when propylene carbonate was used as the electrolyte. The change in temperature did not affect the output voltage of the sensor between 0 and 50 °C. The effect of vibration was demonstrated in this paper.     

A MEMS micromirror fabricated using CMOS post-process

This work describes the fabrication of a micromachined micromirror by the conventional 0.35 μm CMOS process and a simple maskless post-CMOS process. The micromirror contains a rectangular mirror plate and four pairs of serpentine supported beams, is integrated with a 1 × 4 demultiplexer and a four-stage charge pump circuits on a chip. Maskless dry and wet etching processes are the only requirement to suspend the structure. The primary limitation in the fabrication of microstructures has been overcome by the development of a hybrid processing technique, which combines both an anisotropic dry etch and an isotropic wet etch step. A highly reliable wet etching step with high selectivity between aluminum and sacrificial oxide is also reported. Experimental results reveal that the micromirror has a tilting angle of around 5° at operation voltage of 22.5 V and a dynamic response less than 5 ms. The surface properties of the CMOS micromirror, detailed process flows, measurement set-up and the experimental results are also presented in this work.     

A study of an autonomous mobile robot in an outdoor environment

This paper describes an experimental study of the fabrication of micro-mechanisms on a silicon wafer. Planar process technology developed in the industry of CMOS LSI was employed. The structural material is CVD-polycrystalline silicon with a thickness of 2.5 μm and the sacrificial material is CVD-SiO₂ with a thickness of 1.0 μm. In the experimental study, micro-rotors with a shaft and a cap in an assembled form were fabricated on a silicon wafer. The self-alignment process gave a tolerance of 1.0 μm between the rotor and the shaft. The maximum rotation speed observed was 9 x 10⁴ rpm by blowing nitrogen gas.     

An integrated circuit design of a silicon neuron and its measurement results

A novel MOSFET-based silicon nerve membrane model and its measurement results are described in this paper. This model is designed based on a mathematical structure that is characterized by phase plane analysis and bifurcation theory. The circuit is fabricated through MOSIS TSMC 0.35 μm CMOS process. Measurement results demonstrate that our circuit shows fundamental abilities of excitable cells such as a) a resting state, b) an action potential, c) a threshold, and d) a refractoriness. This work was presented in part at the 13th International Symposium on Artificial Life and Robotics, Oita, Japan, January 31–February 2, 2008     

InP dies transferred onto silicon substrate for optical interconnects application

We bonded quantum well InP dies on a photonic layer transferred on silicon CMOS processed wafer using direct molecular bonding. This approach is suitable for new applications, viz., photonics on silicon, 3D packaging and integrated sensors. The chips are diced from a bulk substrate and bonded directly onto a silicon substrate without any organic nor metallic adhesive layer. A thin silicon dioxide layer can be added on both assembled surfaces to enhance bonding quality. After bonding, the dies can mechanically be thinned down to 20 μm and chemically etched. The InAsP quantum well stack of the InP dies keeps its optoelectronics features and performances after being transferred onto a silicon substrate.     

Comparative study of spin coated and sputtered PMMA as an etch mask material for silicon micromachining

SiO₂ and Si₃N₄, are usually used to mask the selected portions during etching of silicon in anisotropic etchants like KOH but polymers are expected to be very good alternative to SiO₂ and Si₃N₄ as masking materials for MEMS applications. An adherent spin coated PMMA layer is reported to work as a mask material. It is a low temperature process, cheaper and films can be easily deposited and removed. One of the problems in its use is its adhesion to the substrate. Our previous experience in the field made us feel that sputtered PMMA will act as better mask because of its better adhesion to silicon. In the present article, a comparative study of spin coated PMMA with sputtered PMMA as an etch mask for silicon micromachining is reported. Structural and adhesive characteristics of the films are determined and compared with those available in the literature. These films deposited on silicon wafer were exposed to anisotropic etchant, KOH, to estimate the masking behavior. The maximum masking time of 32 min in 20 wt.% KOH at 80 °C was obtained for spin coated PMMA samples, which were prebaked at 90 °C. Masking time of sputter deposited PMMA films was found to be 300 min under similar conditions such as 20 wt.% KOH at 80 °C. This masking time is sufficient for fabrication of various MEMS structures, thus indicating candidature of sputtered PMMA as masking material. Various properties of the films are discussed and compared with the ones obtained through literature.     

Silicon condenser microphones with corrugated silicon oxide/nitride electret membranes

Corrugated electret membranes are used in a micromachined silicon microphone. The membranes consist of a permanently corona-charged double layer of silicon dioxide and silicon nitride, known to have excellent charge-storing properties. This electret can replace the external bias needed for condenser microphones. The well-known LOCOS technique—also combined with dry etching—is used for the first time to fabricate membranes with corrugation depths of several microns. The membrane thickness amounts to 600 nm.

The interferometrically measured center deflection is up to 40 nm/Pa for diaphragms with four corrugations of up to 3.3 μm depth and a size of A_M=1 mm². This high mechanical sensitivity limits the dynamic range to sound pressures below 50 Pa. The obtained mechanical sensitivities are in excellent agreement with the theory.

The most compliant corrugated diaphragms result in a microphone sensitivity of 2.9 mV/Pa, an equivalent noise level of 39 dB(A) and a total harmonic distortion below 1.7% at 28 Pa (123 dB SPL). The corrugation depth in the sensors has been only 1.3 μm. All sensors cover the whole audio and low ultrasonic range. The temperature coefficient is between 0.05 and 0.1 dB/K.     

Germanium as a versatile material for low-temperaturemicromachining

Though germanium (Ge) shares many similar physical properties with silicon (Si), it also possesses unique characteristics that are complementary to those of Si. The advantages of Ge include its compatibility with Si microfabrication, its excellent gas and liquid phase etch selectivity to other materials commonly used in Si micromachining, and its low deposition temperature (<350°C) that potentially allows Ge to be used after the completion of a standard CMOS run. Wider applications of Ge as a structural, sacrificial, and sensor material require a more systematic investigation of its processing and properties. The results of such an undertaking are presently reported. The topics covered are the formation of Ge thin films and novel application of the selective deposition of Ge to etch hole filling, characterization of the effects of thermal treatment on the evolution of the residual stress in Ge thin films, etch selectivity for etch mask and sacrificial layer applications, and gas phase release technique for stiction elimination     

Consumer applications: a driving force for high-level synthesis ofsignal-processing architectures

An overview of design alternatives for the translation of signal processing systems into silicon addresses for digital signal processing in consumer applications is presented. Since the most appropriate approach varies with the life-cycle phase of the application, the alternatives range from general-purpose to application-specific approaches. The architectures of the Piramid compiler, which supports digital audio, low-end digital video, telecommunications, speech processing, and control applications, and the Phideo compiler, which supports digital video applications such as HDTV in which sampling rates typically approach the maximum feasible clock rates in state-of-the-art CMOS fabrication processes, are discussed     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

TiO2 thin films from titanium butoxide: Synthesis, Pt addition, structural stability, microelectronic processing and gas-sensing properties

TiO₂ thin films were prepared by spin-coating of a Ti butoxide-derived sol onto oxidized silicon wafers, followed by a heat-treatment at temperatures ranging from 500 to 800 °C. The film thickness after heat-treatment at 500 °C was 50 nm. Pt addition, with a Pt:Ti nominal atomic ratio ranging from 0.01 to 0.1, was achieved by adding solutions of Pt(II) acetylacetonate to the TiO₂ sols. The thin films were investigated by X-ray diffraction, evidencing that Pt promoted the structural transformation of the starting anatase phase of TiO₂ to rutile, with a more enhanced effect with increasing the Pt concentration and/or the heat-treatment temperature. High-resolution transmission electron microscopy evidenced that, when a Pt:Ti atomic ratio of 0.05 and a heat treatment at 500 °C were used, the TiO₂ contained both anatase and rutile phases and interspersed Pt nanocrystals (2–3 nm). This result allowed attributing the structural transformation in TiO₂ to the strain created by the Pt nanocrystals—a conclusion which was further corroborated by the observation that Pd-modified films, prepared under similar conditions, were only composed of anatase TiO₂ and did not contain any Pd nanocrystals. The films heat-treated at 500 °C were able to withstand a full microelectronic processing sequence, including dry etching for gas sensors sensitive area definition, Ti/Pt contact formation, and heater processing on the backside of the sensor substrates. H₂ gas-sensing tests evidenced that the anatase TiO₂ phase was much more sensitive than the rutile one. The presence of Pt further enhanced the gas-sensing properties, lowering the optimum sensor operation temperature to about 330 °C and allowing for the detection of a minimum H₂ concentration of about 1000 ppm.     

Integrating tester pin electronics

A 10-V pin electronics driver that can output signals with low distortion and fast risetimes for both narrow and wide voltage swings is described. The features combine to eliminate the need for dual drivers, pin cards, or test heads, which simplifies the testing of mixed-technology devices or modules. A high-voltages process module has been added to a standard 1.5-μm digital CMOS process, which allows the driver to be in the same silicon as the timing and formatting circuitry. Design and calibration techniques that overcome the limitations of the high-voltage CMOS process are examined     

A novel technique for measuring pico-scale flow rate of a liquid solution using a microchannel

As micrototal analysis system (μ-TAS) becoming more extensively used, techniques for fabricating microchannels, microactuators, and measuring systems are becoming increasingly important. This study describes a novel method for fabricating a closed microchannel that can be used to measure the pico-scale flow rate of a liquid solution with an accuracy of better than 1 pL/s. The flow rate of 9 pL/s is calculated from the measurements. Without any high temperature or high-voltage processing, the microchannel can be integrated in the complementary metal–oxide–semiconductor (CMOS) microfluidic system and the fabricating process involves only some standard CMOS processes and common materials. The batch fabrication of a single integrated circuit (IC) chip is essential to reaching the goal of a system in one chip.     

面向膜电极的选择性生成纳米级多孔硅技术的研究

研究了面向微型燃料电池膜电极的多孔硅薄膜的制备工艺.多孔硅刻蚀工艺高效便宜,与标准CMOS工艺兼容.通过选择不同的衬底掺杂浓度和适当的电解液浓度能控制纳米(或微米)级多孔硅的孔径大小,得到适用于膜电极的纳米级孔径的多孔硅薄膜,证实了纳米级多孔硅可用于硅微燃料电池中膜电极的可能性.     

Synchrony in silicon: the gamma rhythm.

In this paper, we present a network of silicon interneurons that synchronize in the gamma frequency range (20-80 Hz). The gamma rhythm strongly influences neuronal spike timing within many brain regions, potentially playing a crucial role in computation. Yet it has largely been ignored in neuromorphic systems, which use mixed analog and digital circuits to model neurobiology in silicon. Our neurons synchronize by using shunting inhibition (conductance based) with a synaptic rise time. Synaptic rise time promotes synchrony by delaying the effect of inhibition, providing an opportune period for interneurons to spike together. Shunting inhibition, through its voltage dependence, inhibits interneurons that spike out of phase more strongly (delaying the spike further), pushing them into phase (in the next cycle). We characterize the interneuron, which consists of soma (cell body) and synapse circuits, fabricated in a 0.25-microm complementary metal-oxide-semiconductor (CMOS). Further, we show that synchronized interneurons (population of 256) spike with a period that is proportional to the synaptic rise time. We use these interneurons to entrain model excitatory principal neurons and to implement a form of object binding.