Behavioral Modeling Methods for Switched-Capacitor Σ∆ Modulators

Sigma-delta Modulators (SigmaDeltaMs) are cornerstone elements in oversampled analog-to-digital converters and digital-to-analog converters (DAC). Although transistor-level simulation is the most accurate approach known for these components, this method becomes impractical for complex systems due to its long computational time requirements. Behavioral modeling has become a viable solution to this problem. In this paper, we study styles and issues in the accurate modeling of low-power, high-speed SigmaDeltaMs and introduce two new behavioral models for switched-capacitor (SC) integrators. The first model is based on the SC integrator transient response, including the effects of the amplifier transconductance, output conductance, and the dynamic capacitive loading effect on the settling time. The second model is based on a symbolic node admittance matrix representation of the system. Nonidealities such as jitter, thermal noise, and DAC mismatch are also addressed and included in a dual-band, GSM/WCDMA, second-order, multibit SigmaDeltaM model with individual level averaging. VHDL-AMS and MATLAB Simulink were used as modeling languages. Both models are validated against experimental data, showing competitive results in the signal-to-noise-plus-distortion ratio. A comparative analysis between the proposed and a traditional model is presented, with emphasis on the degrading effects due to the integrator dynamics. Moreover, a general simulation speed analysis of the proposed models is addressed.     

Efficient Multibit Quantization in Continuous-Time Σ∆ Modulators

A drawback of continuous-time SigmaDelta modulators is their sensitivity to clock jitter. One way to counteract this is to use a multibit feedback loop which requires a (high resolution) multibit quantizer. However, every extra bit in the quantizer doubles its complexity, power consumption and capacitive load for the analog circuit that needs to drive the quantizer. In this paper a new concept for the quantization in sigma delta modulators is proposed. It allows to significantly reduce the required amount of comparators in the multibit quantizer. Three architectures that realize this new concept are presented and their implementation issues discussed. The architectures' performance has been compared with a conventional modulator through computer simulations. Compared to the conventional modulator, the proposed architectures achieve the same performance, with much less comparators in the quantizer     

A Power Optimized Continuous-Time ∆Σ ADC for Audio Applications

We present design considerations for low-power continuous-time modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation.     

Mismatch Insensitive Double-Sampling Quadrature Bandpass Σ∆ Modulation

In a double-sampling quadrature bandpass sigma-delta modulator, path mismatch between the double-sampling branches and between the I/Q paths occurs. In this paper, an analytical study is presented which shows that this causes quantization noise and input signals to fold from the image band into the signal band and that this also results in a self-image component. To reduce the folding from the image band, a novel resonator is presented. This resonator has a bilinear input circuit so that noise and signals exhibits first-order shaping before folding in the band of interest. Next, three different modulator architectures based on the novel resonator are introduced. Finally, the remaining problem of self-image is tackled with a simple, yet efficient offline calibration strategy. Various design examples are shown and simulated to illustrate and prove the effectiveness of the proposed architectures and methods.     

Efficient Look-Up-Table-Based Modeling for Robust Design of Σ∆ ADCs

The sigma-delta (SigmaDelta) analog-digital converter (ADC) has been widely used in data conversion applications due to its good performance. However, oversampling and complex circuit behaviors render the transistor-level analysis of these designs prohibitively time consuming. The inefficiency of the standard simulation approach also rules out the possibility of analyzing the impacts of a multitude of environmental and process variations critical in modern VLSI technologies. We present a look-up table (LUT)-based modeling technique to facilitate much more efficient performance analysis of SigmaDelta ADCs. Various transistor-level circuit nonidealities are systematically characterized at the building block level and the whole system is simulated much more efficiently using these building block models. Our approach can provide up to four orders of magnitude runtime speedup over SPICE-like simulators, hence significantly shortening the CPU time required for evaluating system performances such as signal-to-noise-and-distortion ratio. The proposed modeling technique is further extended to enable scalable performance variation analysis of complex SigmaDelta ADC designs. Such modeling approach allows us to perform trade-off analysis of various topologies considering not only nominal performances but also their variabilities. Equally important, with our efficient parametric modeling technique, we are able to feasibly extract simulation-based statistical performance correlation models allowing low-cost alternate linearity test of ADC designs.     

A Novel ∆Σ Control System Processor and Its VLSI Implementation

This paper describes a novel control system processor architecture based on DeltaSigma modulation known as the DeltaSigma -CSP. The DeltaSigma -CSP utilizes 1-bit processing which is a new concept in digital control applications with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional-negate-and-add (CNA) unit is instead used for operations in control law implementations. For this reason, the proposed processor has a very small silicon footprint and runs at very high frequencies making it ideal for high-sampling rate, real-time control applications. A number of DeltaSigma -CSP configurations have been implemented as VLSI hard macros in a high-performance 0.13-mum CMOS process and a particular configuration achieved a post-route operating frequency of 355 MHz resulting in a 2.17 MHz sampling rate for a fourth-order control law implementation. Additional results prove that the DeltaSigma -CSP compares very favorably, in terms of silicon area and sampling rates, to two other specialized digital control processing systems, including direct, hardwired implementation of control laws; at the same time, it substantially outperforms software implementations of control laws running on very wide, general-purpose VLIW architectures.     

∆Σ PLL Transmitter With a Loop-Bandwidth Calibration System

We developed a DeltaSigma PLL transmitter with a linear charge pump and a new loop-bandwidth calibration system that can calibrate loop bandwidth accurately in a very short time. The calibration system uses a double integration technique that integrates the transient signal at the voltage-controlled oscillator output during the response to a step wave input to the divider. In our DeltaSigma PLL transmitter for GSM phones, the calibration system keeps the loop bandwidth within 2% and the calibration time is about 25 mus. To improve the GSM spectrum, we developed a charge pump that reduces a spike noise and the asymmetry of the charge and discharge characteristics. The phase error of modulation in the DeltaSigma PLL transmitter with the charge pump and calibration system was kept within 2 degrees rms, and after calibration the 400-kHz offset noise level of the spectrum mask was -64 dBc.     

An Injection-Locked Frequency-Tracking Σ∆ Direct Digital Frequency Synthesizer

A bandpass (BP) sigma-delta modulator (SigmaDeltaM)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BPSigmaDeltaM, shaping quantization noise out of the signal band. The single-bit BPSigmaDeltaM is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BPSigmaDeltaM out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BPSigmaDeltaM-based synthesizer is fabricated in a 0.25-mum digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than -105 dBc/Hz at a 10-kHz offset is achieved     

Impact of Sampling Clock Phase Noise on Σ∆ Frequency Discriminators

SigmaDelta frequency discriminators (SigmaDeltaFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a SigmaDeltaFD's spurious-free dynamic range (SFDR) is derived. It is shown that for SigmaDeltaFDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used SigmaDeltaFDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB.     

Generalized Comb Decimation Filters for Σ∆ A/D Converters: Analysis and Design

This paper addresses the design of generalized comb decimation filters, proposing some novel decimation schemes tailored to SigmaDelta modulators. We present a mathematical framework to optimize the proposed decimation filters in such a way as to increase the SigmaDelta quantization noise (QN) rejection around the so called folding bands, frequency intervals whose QN gets folded down to baseband because of the decimation process. Comparisons are given in terms of passband drop and selectivity with respect to classic comb filters with orders ranging from 3 to 6. As far as the practical implementation of the proposed filters is concerned, we present two different architectures, namely a recursive and a nonrecursive implementation, the latter of which constitutes the basis for realizing multiplier-less generalized comb filter (GCF) realizations. We propose a mathematical framework for evaluating the sensitivity of GCFs to the approximation of the multipliers embedded in the filter architectures. The considerations deduced from the sensitivity analysis, pave the way to an optimization algorithm useful for approximating the multipliers with power-of-2 coefficients     

A Subsampling Quadrature Σ∆ Modulator Based on Distributed Resonators for Use in Radio Receiver

The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma-delta (SigmaDelta) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass SigmaDelta modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require quadrature mixers. Instead, the quadrature mixing is replaced by suitably choosing the sampling instants inside the loop. Two practical circuit implementations are proposed. The first one uses separate circuitry for the I and Q paths. The second architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The proposed modulator may be feasible for the typical IF frequencies used in cellular base stations.     

A 2.5-V 14-bit, 180-mW Cascaded Σ∆ ADC for ADSL2+ Application

This paper presents a sigma-delta (SigmaDelta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 SigmaDelta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 d 15 and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-mum CMOS technology, in a 2.8 mm² active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.     

A Low-Noise 40-GS/s Continuous-Time Bandpass ∆Σ ADC Centered at 2 GHz for Direct Sampling Receivers

This paper presents a 40-GS/s continuous-time bandpass DeltaSigma analog-to-digital converter centered at 2 GHz for wireless base station applications. The ADC consists of a fourth-order loop with multiple feedback and is designed entirely in the s-domain. The circuit achieves an SNDR of 55 dB and 52 dB over bandwidths of 60 MHz and 120 MHz, respectively, and an SFDR of 61dB with a single-ended IIP3 of +4 dBm. The center frequency is tunable from 1.8 to 2 GHz. It employs a G_m-LC_VAR filter based on a MOS-HBT cascode transconductor with an NFMIN of 2.29 dB. The entire circuit is implemented in a 130-nm SiGe BiCMOS technology with 150-GHz f_T SiGe HBT and dissipates 1.6 W from a 2.5-V supply     

A 2.7-mW 2-MHz Continuous-Time Σ∆ Modulator With a Hybrid Active–Passive Loop Filter

In this paper, passive continuous-time (CT) Sigma Delta modulators are briefly reviewed and compared with conventional active CT Sigma Delta modulators. A fifth-order CT Sigma Delta modulator with a hybrid active-passive loop filter is realized with only three active integrators. The hybrid CT Sigma Delta modulator is robust to the excess loop delay, clock jitter, and RC product variations. The prototype chip is designed in a 0.25- mum CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype Sigma Delta modulator achieves a 68-dB dynamic range and a - 75 dB IM3 over a 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.     

A 375-mW Quadrature Bandpass ∆Σ ADC With 8.5-MHz BW and 90-dB DR at 44 MHz

A quadrature bandpass DeltaSigma ADC for a multistandard TV tuner achieves a total dynamic range of 90 dB over an 8.5-MHz passband centered on 44 MHz while consuming 375 mW. The fourth-order continuous-time ADC uses active-RC resonators configured in a modified feedforward architecture     

An IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulator's high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulator's spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm². It consumes 210 mW from a 1.8-V supply     

A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.     

Design Methodology for ΣΔM

The paper presents a design methodology based on correspondence between performance requirements, mathematical parameters, and circuit parameters of a sigma-delta modulator. This methodology will guide a design engineer in selecting the circuit parameters based on system requirements, in translating paper design directly into LSI design, in predicting the effect of component sensitivity, and in analyzing the operations of the sigma-delta modulator. The sigma-delta modulator is viewed as a device which distributes the noise power, determined by peak SNR, over a much broader band, compared to signal bandwidth, shapes and amplifies it, and allows filtering of the out-of-band noise. The shaping and amplification are quantified by two parameters,FandP, whose product is analogous to the square of step size of a uniform coder. These two parameters are related, on one hand, to the time constants or location of zero and poles. On the other hand, inequalities are set up between performance parameters, like signal-to-noise ratio and dynamic range, andFandP.     

Multibit Σ–∆ PWM Digital Controller IC for DC–DC Converters Operating at Switching Frequencies Beyond 10 MHz

An integrated digital controller for dc-dc switch-mode power supplies (SMPS) used in portable applications is introduced. The controller has very low power consumption, fast dynamic response, and can operate at programmable constant switching frequencies exceeding 10 MHz. To achieve these characteristics, three novel functional blocks, a digital pulse-width modulator based on second-order sigma-delta concept (Sigma-Delta DPWM), dual-clocking mode compensator, and nonlinear analog-to-digital converter are combined. In steady state, to minimize power consumption, the controller is clocked at a frequency lower than SMPS switching frequency. During transients the clock rate is increased to the switching frequency improving transient response. The controller integrated circuit (IC) is fabricated in a standard 0.18-mum process and tested with a 750-mW buck converter prototype. Experimental results show the controller current consumption of 55 muA/MHz and verify closed-loop operation at programmable switching frequencies up to 12.3 MHz. Simulation results indicating that this architecture can potentially support operation at switching frequencies beyond 100 MHz are also presented.