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多芯片组件热分析技术研究 总被引:13,自引:0,他引:13
多芯片组件(MCM)是实现电子系统小型化的重要手段之一。由于封装密度大、功耗高,MCM内部热场对器件的性能和可靠性的影响日益严重。文章讨论了MCM内部热场影响器件可靠性的机理,比较了MCM热场计算的方法和特点,研究了有限元分析的方法和求解过程,进行了实际计算,并提出了几种有效的降低MCM结温的方法。 相似文献
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多芯片组件测试方法 总被引:1,自引:0,他引:1
董志凌 《电子工业专用设备》1994,23(4):50-57
由于每个组件的独特设计,多芯片组件(MCM)的测试不仅涉及到MCM硬件测试,而且还涉及到每个设计的电、热性能的分析评估。在制做MCM之前,评估其预定性能需进行综合分析。MCM测试方法包括一个原理简图、组件模拟、结构设计的CAD接口系统和一个既能提供专门功能AC测试能力,又能对各个设计的电、热性能进行分析的测试程序。MCM界所面临的最大问题之一是使用外购芯片。当使用外来芯片或代理商提供的芯片时,会带来芯片测试精度及预测组件合格率等诸多问题。一旦高级的MCMs采用现代工艺开发成功,那么必须建立起分选高级芯片的各种测试方法。本文讨论了对现存的MCM测试进行确定和检验的测试装置并,有助于解决未来MCMs测试所需的方法。 相似文献
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《Microelectronics Reliability》2015,55(5):822-831
The thermal mode analysis is used in this paper to optimize the thermal management with optimal locations and chip sizes for multi-chip package. The average thermal resistance is defined and analyzed. The spreading thermal resistance can be expanded into Fourier series so that the thermal modes can be established. For the infinite thermal modes, only a few terms are needed to be considered due to the rapid convergence of solution. The optimal locations and chip sizes can then be determined by using the first few modes to reduce the thermal resistance as minimal as possible. The optimal locations have the cosine wave property so that the wave nodes might be the suitable sites. On the other hand, the optimal chip sizes have the cardinal sine property which decays monotonously. For given optimal locations, the optimal chip sizes are determined by certain modes. These special modes can be used to analyze the range of optimal locations and chip sizes. 相似文献
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用反射模式的超声波显微镜对系统级封装SIP和多芯片MCM封装模块的品质进行了研究。探测封装内部的分层、裂纹和气泡等间隙类缺陷。用超声探测转换器把脉冲超声波送入样品,同一个转换器把接收到的回声转换成像点。最大的反射振幅是从固体与气体间的界面产生的。在固体材料内部,分层、孔洞及裂纹会造成最大振幅的回声并可以成像。超声波显微镜可发现SIP和MCM样品内间隙类的缺陷分层裂纹和气泡。 相似文献
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Robert Darveaux Lih-Tyng Hwang Arnold Reisman Iwona Turlik 《Journal of Electronic Materials》1989,18(2):267-274
Two-dimensional finite difference computer simulations were used for thermal analysis of an advanced multi-chip package design.
In order to model high performance VLSI and ULSI applications, power dissipations ranging from 10 to 40 W/cm2 on each chip and zero to 5 W/cm2 on the substrate were simulated. It was found that heating due to resistive losses in the thin film interconnections between
chips can impact package thermal performance. The calculated device-to-water thermal resistance was 0.4° C/W and the worst
case chip-to-chip temperature variation was less than 22° C. This excellent thermal performance illustrates the effectiveness
of the package’s water cooled heat sink with direct backside contact to each die. Methods to improve thermal performance are
discussed. 相似文献
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Chan-Su Yun Malberti P. Ciappa M. Fichtner W. 《Advanced Packaging, IEEE Transactions on》2001,24(3):401-406
The insulated gate bipolar transistor (IGBT) modules are getting more accepted and increasingly used in power electronic systems as high power and high voltage switching components. However, IGBT technology with high speed and greater packaging density leads to higher power densities on the chips and increases higher operating temperatures. These operating temperatures in turn lead to an increase of the failure rate and a reduction of the reliability. In this paper, the static and dynamic thermal behavior of IGBT module system mounted on a water-cooled heat sink is analyzed. Although three-dimensional finite element method (3-D FEM) delivers very accurate results, its usage is limited by an imposed computation time in arbitrary load cycles. Therefore, an RC component model (RCCM) is investigated to extract thermal resistances and time constants for a thermal network. The uniqueness of the RCCM is an introduction of the time constants based on the Elmore delay, which represents the propagation delay of the heat flux through the physical geometry of each layer. The dynamic behavior predicted by the thermal network is equivalent to numerical solutions of the 3-D FEM. The RCCM quickly offers insight into the physical layers of the components and provides useful information in a few minutes for the arbitrary or periodic power waveforms. This approach enables a system designer to couple the thermal prediction with a circuit simulator to analyze the electrothermal behavior of IGBT module system, simultaneously 相似文献
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《Microelectronics Reliability》2015,55(1):138-142
The temperature distribution on a ceramic substrate with a small heating element in the middle has been measured by infrared thermography. By comparing the experimental data with a theoretical analysis, the thermal conductivity could be easily obtained. 相似文献
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Ü. Özgür X. Gu S. Chevtchenko J. Spradlin S. -J. Cho H. Morkoç F. H. Pollak H. O. Everitt B. Nemeth J. E. Nause 《Journal of Electronic Materials》2006,35(4):550-555
Thermal conductivities (κ) of melt-grown bulk ZnO samples thermally treated under different conditions were measured using
scanning thermal microscopy. Samples annealed in air at 1050°C for 3 h and treated with N-plasma at 750°C for 1 min. exhibited
κ=1.35±0.08 W/cm-K and κ=1.47±0.08 W/cm-K, respectively. These are the highest values reported for ZnO. Atomic force microscopy
(AFM) and conductive-AFM measurements revealed that surface carrier concentration as well as surface morphology affected the
thermal conductivity. 相似文献
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实验利用瞬态电热技术测量出镀在聚酰亚胺(PI)基底表面的6. 4 nm金薄膜面内方向的导热系数、导电系数和洛伦兹数,并研究了PI薄膜基底的热处理温度与时间对金薄膜导热、导电性能的影响。研究结果表明,PI基底可以促进金薄膜面内方向的热传导与电传导。PI薄膜基底表面金薄膜导热、导电性能最强,适合应用在柔性电子领域中。当对PI薄膜基底的热处理时间为1 h时,随着热处理温度从50℃升到200℃,金薄膜的导热、导电系数呈下降趋势。当热处理温度为200℃时,随着热处理时间从0 h升到6 h,金薄膜的导热、导电性能先下降后上升,并在6 h后趋于稳定。 相似文献