A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum² low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.     

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum² 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.     

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{min}$ Lowering Techniques and Deep Sleep Mode

A voltage scalable 0.26 V, 64 kb 8T SRAM with 512 cells per bitline is implemented in a 130 nm CMOS process. Utilization of the reverse short channel effect in a SRAM cell design improves cell write margin and read performance without the aid of peripheral circuits. A marginal bitline leakage compensation (MBLC) scheme compensates for the bitline leakage current which becomes comparable to a read current at subthreshold supply voltages. The MBLC allows us to lower ${rm V}_{min}$ to 0.26 V and also eliminates the need for precharged read bitlines. A floating read bitline and write bitline scheme reduces the leakage power consumption. A deep sleep mode minimizes the standby leakage power consumption without compromising the hold mode cell stability. Finally, an automatic wordline pulse width control circuit tracks PVT variations and shuts off the bitline leakage current upon completion of a read operation.      

High-performance subquarter-micrometer gate CMOS technology

A single phosphorous-doped poly(n⁺)-Si gate, a 3.5-nm-thick gate oxide, and a retrograde twin-well structure with trench isolation are used in the devices considered. Latchup holding voltages exceed 8 V. The transconductances of 0.22-μm-gate-length n and p MOSFETs are 450 and 330 mS/mm, respectively, and unloaded ring oscillator delays are 36 ps at 2 V. A static-type 1/2 divider utilizing nMOSFETs of 0.16-μm gate length and pMOSFETs of 0.22-μm gate length achieved a maximum operating frequency of 1.3 GHz and power of 5.6 mW at a supply voltage of 2 V     

Low voltage circuit design techniques for battery-operated and/orgiga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q_s) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-μm CMOS process. The chip size is 7.9×16.7 mm² and cell size is 1.35×2.8 μm²     

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

This paper describes an 8 Mb SRAM test chip that has been designed and fabricated in a 45 nm Silicon-On-Insulator (SOI) CMOS technology. The test chip comprises of sixteen 512 kb instances and is designed for use as the principal compilable one-port embedded-SRAM block in a 45 nm ASIC library. Challenges associated with SRAM cell design in SOI are overcome and resulted in a cell size of 0.315 mum² . The paper introduces two circuit techniques that address the AC and DC power consumption issues facing today's embedded-SRAMs. The first technique addresses AC power dissipation by utilizing a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 68% improvement in read power under constant voltage and frequency compared to the previous generation macro . The second technique addresses the DC power consumption by introducing a single-device, header based dynamic leakage suppression scheme that reduces total macro leakage power by 38% with no wake-up cycle requirements.     

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.     

A replica technique for wordline and sense control in low-powerSRAM's

With the migration toward low supply voltages in low-power SRAM designs, threshold and supply voltage fluctuations will begin to have larger impacts on the speed and power specifications of SRAM's. We present techniques based on replica circuits which minimize the effect of operating conditions' variability on the speed and power. Replica memory cells and bitlines are used to create a reference signal whose delay tracks that of the bitlines. This signal is used to generate the sense clock with minimal slack time and control wordline pulsewidths to limit bitline swings. We implemented the circuits for two variants of the technique, one using bitline capacitance ratioing in a 1.2-μm 8-kbyte SRAM, and the other using cell current ratioing in a 0.35-μm 2-kbyte SRAM. Both the RAM's were measured to operate over a wide range of supply voltages, with the latter dissipating 3.6 mW at 150 MHz at 1 V and 5.2 μW at 980 kHz at 0.4 V     

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the power consumption of the cell. This shaped wordline pulse results in improved read noise margin without any degradation in access time for small wordline load. The improvement is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during the hold mode, for a short time (depending on the size of boosting capacitance), wordline voltage becomes negative and charges up to zero after a specific time that results in a lower leakage current compared to conventional SRAM. The proposed technique results in at least 2× improvement in read noise margin while it improves write margin by 3× for lower supply voltages than 0.7 V. The leakage power for the proposed SRAM is reduced by 2% while the total power is improved by 3% in the worst case scenario for an SRAM array. The main advantage of the proposed wordline driver is the improvement of dynamic noise margin with less than 2.5% penalty in area. TSMC 65 nm technology models are used for simulations.     

GaN microwave electronics

In this paper, recent progress of AlGaN/GaN-based power high-electron-mobility transistors (HEMT's) is reviewed. Remarkable improvement in performances was obtained through adoption of high Al contents in the AlGaN layer. The mobility in these modulation-doped structures is about 1200 cm².V^-1.s^-1 at 300 K with sheet densities of over 1×10¹³ cm^-2 . The current density is over 1 A/mm with gate-drain breakdown voltages up to 280 V. F_t values up to 52 GHz have been demonstrated. Continuous wave (CW) power densities greater than 3 W/mm at 18 GHz have been achieved     

A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2)latch and its application in a dual-modulus prescaler

A high speed dual-phase dynamic-pseudo NMOS ((DP)²) latch using clocked pseudo-NMOS inverters is presented. Compared to the conventional D-latch, this circuit has a higher maximum operating frequency and consumes lower dynamic power at a given operating frequency. The latch has been demonstrated by utilizing it in the synchronous counter section of a dual-phase dual-modulus prescaler implemented in a 0.8 μm CMOS process. The maximum operating frequency for the prescaler at 3 V supply voltage is 1.3 GHz, while the power consumption is 9.7 mW. This power consumption is significantly lower than those of the previously reported prescalers implemented in 0.8 μm CMOS processes. The 9.7 mW power consumption at 1.3 GHz also compares favorably to the 24 mW power consumption of the 1.75 GHz prescaler using MOS current mode latches implemented in a 0.7 μm CMOS process. A 25% reduction of the maximum operating frequency for a ~60% reduction of the power consumption should be a useful tradeoff     

A single-chip 9-32 mb/s read/write channel for disk-driveapplications

This paper reports on a single-chip read/write channel for disk drive. The integrated circuit implements a peak detector architecture fully compatible with zoned-bit recording applications. The chip contains all the functions needed to implement a high performance read channel, i.e., pulse detector, programmable active filter, servo demodulator, frequency synthesizer, data separator and RLL(1,7) ENDEC. The design has been done in a way that takes full advantage of the features available in a BiCMOS technology to achieve power saving, high speed and immunity to cross-talk from digital to analog. The IC is fabricated in a 1.2 μ BiCMOS technology and has an active area of approximately 28 mm². While operating from a single 5 V supply the power consumption is only 450 mW at 32 Mb/s     

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.     

Techniques to Extend Canary-Based Standby $V_{DD}$ Scaling for SRAMs to 45 nm and Beyond

$V_{DD}$ scaling is an efficient technique to reduce SRAM leakage power during standby mode. The data retention voltage (DRV) defines the minimum $V_{DD}$ that can be applied to an SRAM cell without losing data. The conventional worst-case guard-banding approach selects a fixed standby supply voltage at design time to accommodate the variability of DRV, which sacrifices potential power savings for non-worst-case scenarios. We have proposed a canary-based feedback to achieve aggressive power savings by tracking PVT variations through canary cell failures. In this paper, we show new measured silicon results that confirm the ability of the canary scheme to track PVT changes. We thoroughly analyze the adaptiveness of the canary cells for tracking changes in the SRAM array, including the ability to track PVT fluctuations. We present circuits for robustly building the control logic that implements the feedback mechanism at subthreshold supply voltages, and we derive a new analytical model to help tune the canary cells in the presence of variations. To realistically quantify the potential savings achievable by the canary scheme, we assess the impact of various sources of overhead. Finally, we investigate the performance of the canary based scheme in nanometer technologies, and we show that it promises to provide substantial standby power savings down to the 22 nm node.      

Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

The increased importance of lowering power in memory design has produced a trend of operating memories at lower supply voltages. Recent explorations into sub-threshold operation for logic show that minimum energy operation is possible in this region. These two trends suggest a meeting point for energy-constrained applications in which SRAM operates at sub-threshold voltages compatible with the logic. Since sub-threshold voltages leave less room for large static noise margin (SNM), a thorough understanding of the impact of various design decisions and other parameters becomes critical. This paper analyzes SNM for sub-threshold bitcells in a 65-nm process for its dependency on sizing, V/sub DD/, temperature, and local and global threshold variation. The V/sub T/ variation has the greatest impact on SNM, so we provide a model that allows estimation of the SNM along the worst-case tail of the distribution.     

Power Si-MOSFET operating with high efficiency under low supply voltage

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.     

A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS

A noncoherent 0-16.7 Mb/s ultra-wideband (UWB) receiver using 3-5 GHz subbanded pulse-position modulation (PPM) signaling is implemented in a 90 nm CMOS process. The RF and mixed-signal baseband circuits operate at 0.65 V and 0.5 V, respectively. Using duty-cycling, adjustable bandpass filters, and a relative-compare baseband, the receiver achieves 2.5 nJ/bit at 10^-3 BER with -99 dBm best case sensitivity at 100 kb/s. The energy efficiency is maintained across three orders of magnitude in data rate. For data rates less than 10 kb/s, leakage power dominates energy/bit.     

The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor

The 3-MB on-chip level three cache in the Itanium 2 processor, built on an 0.18-/spl mu/m, six-layer Al metal process, employs a subarray design style that efficiently utilizes available area and flexibly adapts to floor plan changes. Through a distributed decoding scheme and compact circuit design and layout, 85% array efficiency was achieved for the subarrays. In addition, various test and reliability features were included. The cache allows for a store and a load every four core cycles and has been characterized to operate above 1.2 GHz at 1.5 V and 110/spl deg/C. When running at 1.0 GHz, the cache provides a total bandwidth of 64 GB/s.