A 0.18-μm CMOS Balanced Amplifier for 24-GHz Applications

A 24-GHz balanced amplifier (BA) with a 45-dB gain is realized in 0.18-mum CMOS technology. An effective technique, pi-type parallel resonance, is proposed to boost the high-frequency gain of a MOSFET by resonating out the inherent capacitances. The miniaturized lumped-element coupler in the circuit occupies a chip area of only ~2% compared to that of the conventional transmission-line coupler. The BA consumes 123 mW from a supply voltage of 1 V. To the best of the authors' knowledge, the proposed CMOS BA presents the highest gain of 45.0 dB with a chip area of 0.97 times 0.63 mm² (core area: 0.78 times 0.43 mm²) among the published narrowband amplifiers with similar technologies and operation frequencies.     

A 60-GHz Millimeter-Wave Bandpass Filter Using 0.18-μm CMOS Technology

This letter presents the design and implementation of a 60-GHz millimeter-wave RF-integrated-circuit-on-chip bandpass filter using a 0.18-mum standard CMOS process. A planar ring resonator structure with dual-transmission zeros was adopted in the design of this CMOS filter. The die size of the chip is 1.148times1.49 mm². The investigations of sensitivity to the insertion loss and the passband bandwidth for different perturbation stub sizes are also studied. The filter has a 3-dB bandwidth of about 12 GHz at the center frequency of 64 GHz. The measured insertion loss of the passband is about 4.9 dB, and the return loss is better than 10 dB within the passband.     

A 32-GHz Rotary Traveling-Wave Voltage Controlled Oscillator in 0.18-μm CMOS

A millimeter-wave multiphase voltage-controlled oscillator (VCO) is presented. In order to facilitate high-frequency oscillation and to minimize the phase error caused by the device and layout mismatch, a rotary traveling-wave topology based on transmission lines with inductive loading is employed for the circuit implementation. Using a 0.18-mum CMOS process, the fabricated VCO provides half- quadrature output phases at 32 GHz. The measured output power and phase noise at 1-MHz offset are -9 dBm and -108 dBc/Hz, respectively. Operated at a supply voltage of 1.2 V, the power consumption of the proposed circuit is 54 mW.     

A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10^-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.     

An Ultra-Wideband Distributed Active Mixer MMIC in 0.18-μm CMOS Technology

In this paper, a distributed circuit topology for active mixers suitable for ultra-wideband operations is presented. By employing nonuniform artificial transmission lines with the complementary transconductance stages in the Gilbert-cell multiplier, the proposed mixer demonstrates broadband characteristics at microwave frequencies while maintaining a high conversion gain (CG) with improved gain flatness. Using a 0.18-mum CMOS process, the proposed circuit is implemented, exhibiting a -3-dB bandwidth of 28 GHz. With a local-oscillator power of 3 dBm and an IF frequency of 10 MHz, the fabricated circuit has a CG of 12.5plusmn1 dB and an average input third-order intercept point (IIP₃) of 0 dBm within the entire frequency range. The fully integrated wideband mixer occupies a chip area of 0.87times0.82 mm² and consumes a dc power of 20 mW from a 2-V supply voltage     

A Dual-Antenna Phased-Array UWB Transceiver in 0.18-μm CMOS

A dual-antenna ultra-wideband (UWB) transceiver in 0.18-mum CMOS for mode-1 OFDM applications employs the techniques of antenna diversity and integrated RF selectivity to improve robustness to interferers. Optimal selectivity in receiver and band flatness in transmitter are achieved by on-chip calibration of each band. The packaged device achieves an overall noise figure of 4.7 dB, an IIP3 of -0.8 dBm, a TX P1 dB of 3.1 dBm, and an error vector magnitude (EVM) of -27.2 dB for 480 Mb/s. The transmit output spectrum is fully compliant with FCC mask for UWB without any external bandpass filter     

A Ku-Band Frequency Synthesizer in 0.18-μm CMOS Technology

This letter presents a fully integrated frequency synthesizer implemented in a 0.18-mum foundry CMOS process. By employing a modified differential Colpitts voltage controlled oscillator to improve the tuning range and the phase noise, the integer-N frequency synthesizer demonstrates an output frequency from 14.8 to 16.9GHz, allowing wideband operations at Ku-band. Operated at an output frequency of 15GHz, the proposed synthesizer exhibits a reference sideband power of -50dBc and a phase noise of -104.5dBc/Hz at 1-MHz offset. The fabricated circuit consumes a dc power of 70mW from a 2-V supply voltage     

A 50-GHz Phase-Locked Loop in 0.13-μ m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.     

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-μm CMOS T/R Switch

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications     

Millimeter-Wave Bandpass Filters by Standard 0.18-μm CMOS Technology

Millimeter-wave (mm-wave) bandpass filters are presented using the standard 0.18-mum CMOS process. Without any postprocessing steps, thin film microstrip (TFMS) structure is properly constructed on the low-resistivity silicon substrate, aiming at reducing the substrate loss and crosstalk to a large extent. Using the broadside-coupled scheme, a tight coupling is achieved so as to make up a class of low-loss and broadband TFMS bandpass filters in the mm-wave range. To achieve a small size, one-stage and two-stage filters with sinuous-shaped resonators are designed and fabricated. A good agreement between the predicted and measured results has been observed up to 110 GHz     

A 16-GHz Triple-Modulus Phase-Switching Prescaler and Its Application to a 15-GHz Frequency Synthesizer in 0.18-μm CMOS

A triple-modulus phase-switching prescaler for high- speed operations is presented in this paper. By reversing the switching orders between the eight 45deg-spaced signals generated by the 8 : 1 frequency divider, the maximum operating frequency of the prescaler is effectively enhanced. With the triple-modulus switching scheme, a wide frequency covering range is achieved. The proposed prescaler is implemented in a 0.18-mum CMOS process, demonstrating a maximum operating frequency of 16 GHz without additional peaking inductors for a compact chip size. Based on the high-speed prescaler, a fully integrated integer-N frequency synthesizer is realized. The synthesizer operates at an output frequency from 13.9 to 15.6 GHz, making it very attractive for wideband applications in Ku-band. At an output frequency of 14.4 GHz, the measured sideband power and phase noise at 1-MHz offset are -60 dBc and -103.8 dBc/Hz, respectively. The fabricated circuit occupies a chip area of 1 mm² and consumes a dc power of 70 mW from a 1.8-V supply voltage     

A 16–46 GHz Mixer Using Broadband Multilayer Balun in 0.18-μm CMOS Technology

A 16-46 GHz mixer using broadband balun fabricated in standard 0.18-mum CMOS process is demonstrated. The broadside-coupled balun with wide bandwidth and low insertion loss utilizes the inherent 3D multilayer structure in CMOS process. The mixer exhibits radio frequency bandwidth from 16 to 46 GHz with a conversion loss ranging from 13 plusmn 1.5 dB, and achieves bandwidth over 103% with a compact chip size of 0.24 mm².     

Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-μm CMOS

This paper will discuss a number of circuit approaches which lower the power consumed by a current steering digital-to-analog converter while maintaining both DC and AC performance levels. An example design provides 14-bit resolution and 200 MSPS conversion rate in a one-poly four-metal (1P4M) 0.18-mum CMOS process. The inclusion of optional 3.3-V compatible devices allows operation over a supply range from 1.7 to 3.6 V. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8-V operation and as low as 0.28 mW/MSPS at 3.3 V. A measured single-tone SFDR of 70 dB is achieved at a 50-MHz output frequency, with a two-tone IMD of -75 dBc at 71 MHz output.     

A 2.45-GHz 0.13-μm CMOS PA With Parallel Amplification

In this paper, a fully integrated 0.13-mum CMOS RF power amplifier for Bluetooth is presented. Four differential amplifiers are placed on a single chip and their outputs are combined with an on-chip LC balun structure. This technique allows to have a low impedance transformation ratio for each individual amplifier, and thus a lower power loss. The amplifier achieves a measured output power of 23 dBm at a supply voltage of 1.5 V and a drain efficiency of 35% and a global efficiency of 29%. The parallel amplification topology allows to efficiently control the output power which results in an efficiency improvement when the output power is reduced     

A 2.4-GHz Low-Power Low-IF Receiver and Direct-Conversion Transmitter in 0.18-μm CMOS for IEEE 802.15.4 WPAN Applications

In this paper, a low-power low-IF receiver and a direct-conversion transmitter (DCT) suitable for the IEEE standard 802.15.4 radio system at the 2.4-GHz band are presented in 0.18-mum deep n-well CMOS technology. By using vertical NPN (V-NPN) bipolar junction transistors in the baseband analog circuits of the low-IF receiver, the image rejection performance is improved and the power consumption is reduced. In addition, by applying the V-NPN current mirrored technique in a DCT, the carrier leakage is reduced and the linearity performance is improved. The receiver has 10 dB of noise figure, -15 dBm of third-order input intercept point, and 35 dBc of image rejection. The transmitter has more than -2 dBm of transmit output power, -35 dBc of local oscillator leakage, and -46 dBc of the transmit third harmonic component. The receiver and transmitter dissipate 6 and 9 mA from a 1.8-V supply, respectively     

A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-μm CMOS

In this paper, a current-to-voltage combiner is proposed to realize a highly linear, balanced noise-cancelling low-noise amplifier (LNA) capable of low-voltage operation. The current-to-voltage combiner, implemented in the load of the amplifier, converts the output currents of the parallel common-gate (CG) and common-source (CS) stages of the LNA to voltages, equalizes the amplitudes of the voltages, and combines the voltages to a single output voltage. Since only a CS stage and passive components are employed to cancel the noise and distortion due to the CG input impedance matching circuit, high linearity is achieved in spite of the low supply voltage of 1.2 V. The LNA achieves a noise figure (NF) of 3.0 dB at 2.1 GHz with an input-referred third-order intercept point (IIP3) of +10.5 dBm while consuming 10.5 mA from a 1.2-V supply. The amplifier is fabricated in 0.13-mum CMOS process.     

A Low Power Folded Mixer for UWB System Applications in 0.18-μm CMOS Technology

This letter presents a wideband mixer using a commercial 0.18-mum CMOS technology process for ultra-wideband (UWB) system applications. To achieve wideband frequency response and low dc power consumption for UWB system applications, the folded approach is utilized to reduce supply voltage as well as dc power consumption, and wideband input matching network is used to achieve wideband frequency response. The measured results show that the proposed mixer demonstrates a wideband frequency response from 0.2 to 16GHz with a conversion gain of better than 5.3dB. The dc power consumption is 15mW under a supply voltage of 1.8V, with a compact size of 0.68mmtimes0.65mm     

A 46-GHz Direct Wide Modulation Bandwidth ASK Modulator in 0.13-μm CMOS Technology

A 46-GHz direct wide modulation bandwidth amplitude shift keying (ASK) modulator with an embedded voltage controlled oscillator (VCO) is proposed in this letter. This circuit is fabricated using a standard commercial bulk 0.13-mum CMOS technology and exhibits a modulation bandwidth wider than 1 GHz with a chip size of 390 times 480 mum². The recovered time-domain waveform shows a very good eye-pattern opening. To the best of the authors' knowledge, this is the first direct ASK modulator with an embedded VCO in the millimeter-wave regime using CMOS processes.     

A 2.2-μm-Pitch Single-Transistor Charge-Modulation Pixel in a 0.13-μm CMOS Process

This paper presents the investigation of a 2.2-mum-pitch single-transistor pixel designed in a 0.13-mum CMOS process. Based on charge-induced potential variation of the floating-body of the transistor, this single pixel device can be operated to perform photodetection, charge integration, signal readout, and reset. The main electrical characteristics of the pixel are evaluated by device modeling and simulations as well as measurements of test chips. With optimization of process and electrical parameters, testing results show a conversion factor of 47 muV/hole, a charge-handling capability of 3500 holes, a temporal noise of four holes, and a dynamic range of 40 dB.     

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit