Double-Gate Tunnel FET With High-κ Gate Dielectric

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO₂, while the subthreshold slope for fixed values of V_g remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an I_on/I_off ratio of more than 2 times 10¹¹ is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.     

A new polysilicon CMOS self-aligned double-gate TFT technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.     

Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy

In this paper, a simple high performance double-gate metal oxide semiconductor field effect transistor (MOSFET) using lateral solid-phase epitaxy (LSPE) is experimentally demonstrated and characterized. The thin channel of the double-gate MOSFET was obtained using the high quality LSPE crystallized layer. The fabricated double-gate MOSFET provides good current drive capability and steep subthreshold slope, and they are approximately 350 /spl mu/A//spl mu/m (@ V/sub ds/ = 2.5 V and V/sub gs/ - V/sub T/ = 2.5 V) and 78 mV/dec for the devices with 0.5 /spl mu/m channel length. Compared to the conventional single-gate transistor, the double-gate NMOSFET fabricated on the LSPE layer has better V/sub T/ roll-off characteristics, DIBL effect, and 1.72 times higher current drive. The peak effective electron mobility of the LSPE crystallized layer is approximately 382 cm/sup -2//V.s.     

Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

In this work, the lateral electric field distribution in the channel of a double-gate TFT is studied and compared with that of a conventional single-gate TFT. The double-gate TFT is predicted to suffer from a more severe anomalous off-current than the single-gate TFT. A smart double-gate TFT technology is proposed to decrease the off-current. The unique feature of the technology is the lithography independent formation of the self-aligned double-gate and the symmetric lightly doped drain (LDD) structures. With the LDD applied, the anomalous off-current of the fabricated double-gate TFT is reduced by three orders of magnitude from the range of 10/sup -9/ A//spl mu/m to 10/sup -12/ A//spl mu/m. The on/off current ratio is increased by three orders of magnitude accordingly from around 10/sup 4/ to 10/sup 7/.     

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.     

Fabrication and optical-switching results of the double-gate static-induction thyristor with the first planar-gate and the second buried-gate structure

A new thyristor structure-a class of the double-gate (DG) static-induction (SI) thyristors-was fabricated and showed quick dual-gate current controllability and less turn-off tailing current, because the anode current can be controlled by both the first and the second gate and the electrons stored at the second gate can be discharged through the second gate circuit in a very short time at the turn-off process. Moreover, the DG SI thyristors have a capability of lower forward voltage drop and faster switching speed than those values of the single-gate SI thyristor.     

Kink-free polycrystalline silicon double-gate elevated-channelthin-film transistors

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented     

Speed superiority of scaled double-gate CMOS

Unloaded ring-oscillator simulations, performed with a generic process/physics-based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V_DD), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low V_DD < ~1 V     

双栅双应变沟道全耗尽SOI MOSFETs的特性分析

提出了一种全新的器件结构--双栅双应变沟道全耗尽SOI MOSFETs,模拟了沟道长度为25nm时器件的电学特性.工作在单栅模式下,应变沟道(Ge=0.3)驱动能力与体Si沟道相比,nMOS提高了43%,pMOS提高了67%;工作在双栅模式下,应变沟道(Ge=0.3)与体Si沟道相比较,驱动电流的提高nMOS为31%,pMOS为60%.仿真结果表明,双栅模式比单栅模式有更为陡直的亚阈值斜率,更高的跨导以及更强的抑制短沟道效应的能力.综合国内外相关报道,该结构可以在现今工艺条件下实现.     

Manufacturability of single and double-gate ultrathin silicon filmfully depleted SOI technologies

Of several possible devices that can be used for sub-70 nm node technologies, two are built on ultra thin SOI layers. Scaling of such thin silicon layer SOI devices is constrained by the severe short channel control problem. To alleviate this, double-gate structures have been proposed by Wong et al. (1999), Chang et al. (2000), and Ieong et al. (2000). In this paper, we assess the manufacturability of single-gate (SG) and symmetric double-gate (DG) devices for gate lengths between 15 and 70 nm. Our results show that SG devices are not only manufacturable but also have tighter distributions than DG devices; inverter ring oscillator (RO) stage delays and power consumption are also better for SG devices. Besides gate length we find two additional major sources of variation: silicon thickness and encapsulation width. We show that for an optimized double-gate device with minimized parasitic resistance, CD variations become a dominant factor at 20-nm gate lengths despite superior electrostatic integrity. Also, the work function of metal gates must be controlled to better than ±0.1 eV (3σ) to avoid severe manufacturability problems     

Effect of LDD structure and channel poly-Si thinning on agate-all-around TFT (GAT) for SRAM's

A lightly doped drain (LDD) structure was used in a gate-all-around TFT (GAT). This suppresses the leakage current much more than the LDD used in a single-gate TFT (SGT), and the current level of the GAT with the LDD is almost the same as that of the single-gate TFT (SGT) with the LDD keeping the GAT's advantage of a high on-current. This is because the LDD effectively relaxes the electric field at the drain edge and reduces the effect of the electric field from the surrounded gate of the GAT. Furthermore, the GAT can suppress individual performance variations. The suppression mechanism of the individual performance variation in a GAT was investigated using a poly-Si TFT simulator. The thinner the channel poly-Si, the smaller the individual performance variation of the TFT. The GAT is more effective in decreasing the individual performance variation for thin channels than the SGT because the GAT can achieve the full depletion of the channel poly-Si with a channel thickness twice as large as the SGT. The GAT is eminently suitable for use in high-density, low-voltage operations, and low-power SRAM's     

Enhancement of charge storage performance in double-gate silicon nanocrystal memories with ultrathin body structure

We propose double-gate silicon nanocrystal memories (NCMs) with ultrathin body structure. Double-gate NCMs experimentally show larger threshold voltage shift (/spl Delta/V/sub th/) and longer charge retention time than single-gate NCMs. These superior behaviors in double-gate NCMs are explained by the increase in the body potential due to electrons in one side nanocrystals that prevent electrons in the other side nanocrystals from escaping. Thinner transistor body enhances the mutual influence between electrons in both sides. It is also found that the endurance characteristics are also improved by the reduced potential difference in the tunnel oxide.     

Silicide application on gated single-crystal, polycrystalline andamorphous silicon FEAs. I. Mo silicide

In order to improve both the level and the stability of electron field emission, the tip surface of silicon field emitters have been coated with a molybdenum layer of thickness 25 nm through the gate opening and annealed rapidly at 1000°C in inert gas ambient. The gate voltages of single-crystal silicon (c-Si), polycrystalline silicon (poly-Si) and amorphous silicon (a-Si) field emitter arrays (FEAs) required to obtain anode current of 10 nA per tip are 90 V, 69 V, and 84 V, respectively. In the case of the silicide emitters based on c-Si, poly-Si and a-Si, these gate voltages are 76 V, 63 V, and 69 V, respectively. Compared with c-Si, poly Si and a-Si field emitters, the application of Mo silicide on the same silicon field emitters exhibited 9.6 times, 2.1 times, and 4.2 times higher maximum emission current, and 6.1 times, 3.7 times, and 3.1 times lower current fluctuation, respectively. Moreover, the emission currents of the silicide FEAs depending on vacuum level are almost same in the range of 10^-9~10^-6 torr. This result shows that silicide is robust in terms of anode current degradation due to the absorption of air molecules     

A double-gate-type static-induction thyristor

A double-gate-type static-induction thyristor (DG-SIThy) with a high blocking voltage and a high current rating has been fabricated. In this paper, a basic operational mechanism, a fabrication procedure, and the electrical characteristics of the DG-SIThy are described. In the DG-SIThy, both electron injection and hole injection are controlled by signals applied to two gale regions so that the DG-SIThy is capable of higher frequency operations than a single-gate SIThy. In the DG-SIThy, described here, both a cathode and a gate (first gate) regions have been fabricated on one side of a semiconductor wafer and both an anode and gate.(second gate) regions on another side. For realizing the DG-SIThy with a high blocking voltage and a high current rating, we have tried attentively to form a p-n junction on one side of the wafer without influencing the p-n junction on the other side, and have developed a new counter-doping technique for epitaxial growth and an improved package structure for a compression-mounted device. The DG-SIThy fabricated with these techniques has shown a for-Ward blocking voltage of 1000 V, an average current rating of 100 A, and a forward voltage drop of 1.44 V at the rated anode current. A turn-on time of 0.95 its and a turn-off time of 0.48 µs have been observed at the rated anode current and at anode voltages of 650 and 550 V, respectively. As already speculated, the DG-SIThy shows a higher switching speed and a lower forward drop than the single-gate SIThy.     

A new fabrication process of field emitter arrays with submicrongate apertures using local oxidation of silicon

The field emitter arrays with submicron gate apertures for low voltage operation have been successfully fabricated by modifying the conventional Spindt process. The key element of the new process is forming the gate insulator by local oxidation of silicon, resulting in the reduction of the gate hole size due to the lateral encroachment of oxide. The gate hole diameter of 0.55 μm has been obtained from the original mask pattern size of 1.55 μm. An anode current of 0.1 μA per emitter is measured at the gate voltage of about 53 V, while the gate current is less than 0.3% of the anode current. To obtain the same current level from a Spindt-type emitter with the same gate hole diameter as the mask pattern size, a gate bias of about 82 V is needed     

Performance analysis of SiGe double-gate N-MOSFET

The major purpose of this paper is to find an alternative configuration that not only minimizes the limitations of single-gate (SG) MOSFETs but also provides the better replacement for future technology. In this paper, the electrical characteristics of SiGe double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si double-gate N-MOSFET. Furthermore, in this paper the electrical characteristics of Si double-gate N-MOSFET are demonstrated and compared with electrical characteristics of Si single-gate N-MOSFET. The simulations are carried out for the device at different operational voltages using Cogenda Visual TCAD tool. Moreover, we have designed its structure and studied both I_d-V_g characteristics for different voltages namely 0.05, 0.1, 0.5, 0.8, 1 and 1.5 V and I_d-V_d characteristics for different voltages namely 0.1, 0.5, 1 and 1.5 V at work functions 4.5, 4.6 and 4.8 eV for this structure. The performance parameters investigated in this paper are threshold voltage, DIBL, subthreshold slope, GIDL, volume inversion and MMCR.     

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

Simulation of nanoscale MOSFETs using modified drift-diffusion and hydrodynamic models and comparison with Monte Carlo results

The dc behavior of single-gate and double-gate MOSFETs with gate lengths ranging from 5 to 100 nm is simulated using drift-diffusion, hydrodynamic, and Monte Carlo approaches. It is shown that by simple adjustments of the drift-diffusion and hydrodynamic transport model parameters the Monte Carlo currents can be reproduced in the entire gate length range. The suitability of the different simulation methods for the simulation of nanometer MOSFETs is briefly discussed.     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

Fully depleted double-gate MSDRAM cell with additional nonvolatile functionality

We demonstrate a new fully depleted (FD) double-gate (DG) MSDRAM cell, which features SONOS type storage node at the back-gate (control-gate). This single-transistor cell, based on the meta-stable dip (MSD) hysteresis effect, can also be operated in non-volatile memory (NVM) mode. The NVM functionality is achieved by Fowler–Nordheim tunneling hole injection into the nitride storage node; the injected holes induce a permanent inversion layer in silicon body. The proposed device shows a large current ratio between ‘1’ and ‘0’ states (～10³) and a wide memory window (～3 V). The effect of the NVM functionality on the MSD hysteresis was investigated and combined with the effect of the control-gate bias. The SONOS charging can be used for replacing the second gate (i.e. enabling single-gate MSDRAM) or for achieving ‘unified’ memory operation.