Electrical characteristics of 500-bit Al-Al2O3-Al CCD shift registers

Double-level metallization (Al-Al2O3-Al) 64-b and 500-b linear, n-channel, surface-channel charge-coupled device (CCD) shift registers (with 929 µm²(1.44 mil²) area per bit) show charge transfer efficiencies of 99.98 percent at 1-MHz data rates. Results indicate advantages for the Al-Al2O3-Al metallization system in ease of fabrication, reliability, clocking, charge carrying capability, and high-speed operation of large arrays.     

A 64-kbit block addressed charge-coupled memory

This paper describes the design and performance of a 64-kbit (65 536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories. The memory chip is organized as 64K words by 1 bit in 16 blocks of 4 kbits. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. The chip is fully decoded with write/recirculate control and two-dimensional decoding to permit memory matrix organization with X-Y chip select control. All inputs and the ouput are TTL compatible. Operated at a data rate of 1 MHz, the mean access time is about 2 ms and the average power dissipation is 1 µW/bit. The maximum output data rate is 10 MHz, giving a mean access time of about 200 µs, and an average power dissipation of 10 µW/bit. The memory chip is fabricated using an n-channel polysilicon gate process. Using tolerant design rules (8-µm minimum feature size and ±2-µm alignment tolerance) the CCD cell size is 0.4 mil²and the total chip size is 218 × 235 mil². The chip is mounted in a 22-pin 400-mil wide ceramic dual in-line package.     

A 16-kbit block addressed charge-coupled memory device

This paper describes the design and performance of a 16- kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 µW/bit with another 0.5 µW/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.     

A 16 384-bit high-density CCD memory

A 16 384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 3.45 × 4.29 mm²(136 × 169 mil²), fits a standard 16-pin package, and is organized as four separate shift registers of 4096 bits, each with its own data input and data output terminals. A two-level polysilicon gate n-channel process was used for device fabrication. A condensed serial-parallel-serial (CSPS) structure was found to provide the highest packing density. Only two external clocks are required driving capacitances of 60 pF each at one-half the data transfer rate. Operations at data rates of 100 kHz to 10 MHz have been demonstrated experimentally, the on-chip power dissipation at 10 MHz being less than 20 µW/bit.     

Rejection characteristics in a video-signal processor using CCD comb filters

This paper describes charge-coupled device (CCD) combfilter rejection characteristics in the video bandwidth. Notch-frequency shifts and rejection-ratio decreases are caused by the incomplete charge transfer in the CCD channel and also by timing error in the charge sampling, which shorten the effective delay time from the ideal 1Hperiod. In the 1H comb filters, 30-dB rejections are achieved within the 4.5-MHz bandwidth for less than 2 × 10^-5per transfer inefficiency. The timing error in the input section can be compensated for by adjusting the input-gate biasing voltage. The analyses are extended to the 2Hcomb filter constructed with three identical CCD's. The 1.2 × 10^-4inefficiency, which is six times as large compared with that in the 1Hfilter, is allowable to maintain the 30-dB ratio. The rejection is shown to be constant when the product of the inefficiencies in the series-connected CCD's is constant. The experimentally obtained results suggest the analyses are reasonable.     

Design of a 16 384-bit serial charge-coupled memory device

This paper describes a 16 384-bit serial charge-coupled memory device designed primarily for low cost and compatibility with existing high-volume manufacturing techniques. To obtain low access time, the device was organized as 64 recirculating shift registers each 256 bits long. Any one register can be selected at random for reading or writing, by means of a 6-bit address input. The alternatives considered in choosing the charge-coupled device (CCD) structure and chip organization are discussed. Data regeneration circuits are described in detail. The device was fabricated on a silicon chip, with an area of 2.07 mil²/bit (including all peripheral circuitry). It operates at data rates exceeding 2 MHz, and has a minimum average access time of under 100 µs.     

Charge-transfer efficiency in a buried-channel charge-coupled device at very low signal levels

A measurement of charge-transfer efficiency (CTE) is described for a 256-element charge-coupled linear imaging device operated below room temperature and at a very low total charge level per charge packet, that is, at a level of approximately 1/20 000th of saturation. This measurement was carried out at a register frequency near 15.75 kHz, the standard television-line frequency. CTE was measured by noting the dependence of the size of the principal charge packet upon the number of transfers. It was observed that at a dark current level of 4 electrons per packet and a photosignal level of 15 electrons the signal loss through approximately 250 transfers was 1 ± 5 electrons at the 50 percent confidence level. A signal-averaging technique was used to obtain this small probable error in the measurement. An analysis has been performed which assumes bulk trapping as the limiting mechanism and from which it may be concluded that to the same probable error the bulk-trap concentration in the CCD channel region is less than 4 × 10¹²cm^-3for trap energies in the range between 0.23 and 0.32 eV below the conduction band. This result demonstrates the possibility of developing a 500 × 500 element charge-coupled imaging device which would have satisfactory CTE for signal levels as low as approximately 10 electrons per picture element.     

A 64-bit 800-MHz insulated-gate CCD on InP

Sixty-four-bit 259-gate insulated gate buried-channel charge-coupled devices (CCD's) have been fabricated on semi-insulating InP using a planar ion implantation process. These 5-µm gate-length structures, exercised with sinusoidal clocks, have operated to a measurement-limited upper frequency of 800 MHz and exhibited average effective stored charge per unit area in their channels as high as 6 × 10¹²electrons cm^-2. Input-to-output delay-time measurements as a function of frequency clearly indicate proper CCD operation.     

Counting of deep-level traps using a charge-coupled device

Quantization in dark current generation has been observed for the first time through the use of a virtual-phase charge-coupled device. Two sites for bulk silicon dark current have been identified with capture cross sections of 1.8 × 10^-15cm²and 5.4 × 10^-16cm², and concentrations of 1.3 × 10⁹cm^-3and 1.5 × 10⁸cm^-3, respectively.     

A novel quadrilinear CCD for high resolution line arrays

This paper presents a novel quadrilinear CCD, allowing both serial and parallel clocking with one set of busbars common to inner and outer registers on the same side of the array. This is made possible by the special organization of the charge transfer from inner to outer registers. Line arrays having 384, 808, 1728, and 3456 sensors have been fabricated successfully on a pitch of 8 µm; the sensor nonuniformity is less than ±5 percent and the transfer loss is 1.10^-5in both inner and outer registers.     

Hybrid IRCCD imaging array

A hybrid IRCCD for high background application has been successfully fabricated. The device consists of fifty Hg0.7Cd0.3Te detector diodes of 50-µm × 50-µm sensitive areas and a silicon CCD maltiplexer with input circuits on 40-µm centers having bucket background subtraction and blooming protection circuits. The noise-equivalent power (NEP) of the IRCCD is 5 × 10^-14W-Hz^-1/2at background photon flux level of 4 × 10¹⁵photons . cm^-2s^-1, integration time of 2 × 10^-5s, and clock frequency of 3 × 10⁶Hz. The noise source of the detector diodes limits the IRCCD performance. The IRCCD is also evaluated with the real-time raster-scanned thermal images displayed on a CRT monitor. Two-dimensional images are generated by using a scanning mirror. A fixed-pattern noise is reduced by comparison of an object video to the reference video stored in a memory. A noise-equivalent temperature difference of the system is 0.6°C at a frame rate of 30 Hz. Instantaneous field of view is 1 mrad × 1 mrad and the field of view of the system is 12° × 5.7°.     

A nonvolatile charge-addressed memory (NOVCAM) cell

A nonvolatile charge-addressed memory (NOVCAM) cell is described in a 64-bit shift register configuration. The charge address is performed by a charge-coupled device (CCD) shift register and the information is stored in metal-nitride-oxide-silicon (MNOS) nonvolatile sites located in parallel with the CCD shift register. The tunneling electric field strength across the thin-oxide MNOS structure is controlled by the magnitude of the charge transferred from the CCD register. The write, erase, and read modes of operation are discussed with typical /spl plusmn/20 V 10 /spl mu/s write/erase, and 2 V 2 /spl mu/s read conditions. Readout is accomplished by parallel stabilized charge injection from a diffused p/n junction to minimize access time to the first bit.     

Modeling of charge transfer by surface acoustic waves in a monolithic metal/ZnO/SiO2/Si system

This paper discusses modeling of minority-carrier charge transfer by surface acoustic waves (SAW's). An idealized, structure independent model which includes the mechanism of carrier diffusion is described and definitions of charge-transfer efficiency and charge capacity analogous to those of a conventional charge-coupled device are introduced and developed. The model is used to predict the fundamental upper limit performance of the device in the absence of surface-state trapping and bulk recombination generation. The parameters of the model are evaluated for the monolithic metal/ZnO/SiO2/Si system, and the model is used to predict charge distributions and charge capacity for surface wave frequencies in the range of 40 MHz to 2 GHz. At high frequencies, the predicted device performance is found to be limited by carrier diffusion and the SiO2thickness.     

Free charge transfer in charge-coupled devices

The free charge-transfer characteristics of charge-coupled devices (CCD's) are analyzed in terms of the charge motion due to thermal diffusion, self-induced drift, and fringing field drift. The charge-coupled structures considered have separations between the gates equal to the thickness of the channel oxide. The effect of each of the above mechanisms on charge transfer is first considered separately, and a new method is presented for the calculation of the self-induced field. Then the results of a computer simulation of the charge-transfer process that simultaneously considers all three charge-motion mechanisms is presented for three-phase CCD's with gate lengths of 4 and 10 µ. The analysis shows that while the majority of the charge is transferred by means of the self-induced drift that follows a hyperbolic time dependence, the last few percent of the charge decays exponentially under the influence of the fringing field drift or thermal diffusion, depending on the design of the structure. The analysis shows that in CCD's made on relatively high resistivity substrates, the transfer by fringing-field drift can be very fast, such that transfer efficiencies of 99.99 percent are expected at 5- to 10- MHz bit rates for 10-µ gate lengths and at up to 100 MHz for 4-µ gate lengths.     

A 16-kbit Block Addressed Charge-Coupled Memory Device

This paper describes the design and performance of a 16-kbit charge-coupled serial memory device. The memory is organized in four blocks of 4 kbits each with on-chip decoding and is mounted in a 16-pin ceramic dual-in-line hermetic package. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. Operated at a data rate of 1 MHz the mean access time is 2 ms and the on-chip power dissipation is calculated to be 1.5 /spl mu/W/bit with another 0.5 /spl mu/W/bit being required in off-chip clock drivers. The maximum designed output data rate is 10 MHz. Compared to the serpentine and loop organized memory charge-coupled device (CCD), the SPS organization has the advantages of lower power dissipation, greater tolerance to process parameter variations, and higher output data rate. All inputs and outputs are TTL compatible. Write/recirculate control is provided on the chip as well as two-dimensional decoding to permit memory matrix organization with X, Y chip select control. All the on-chip peripheral circuits use dynamic MOS circuitry to minimize power consumption. The charge sensing on the chip is achieved with balanced regenerative sense amplifiers. The memory array uses the three-phase three-level polysilicon electrode structure, and the chip is fabricated using an MOS n-channel polysilicon gate process with self-aligned source, drain, and channel stop.     

Surface potential equilibration method of setting charge in charge-coupled devices

A method of setting charge in a charge-coupled device (CCD) is described whereby the input diode is suitably pulsed and an amount of charge is retained in a potential well under the first transfer electrode. It is shown that, within limits defined by the operating potentials of the device, the sizes of the generated charge packets are linearly dependent on the voltage difference between the first transfer electrode and the input gate. They are also independent of threshold voltage. The method has important applications in all CCD's where it is necessary to obtain a linear low noise charge input that is uniform from one device to another. The linearity has been demonstrated with a 64-element CCD which with a sinusoidal input shows second and third harmonics to be 40 dB down from the fundamental. Measured rms input noise was above the minimum theoretically achievable value but was still 80 dB down from the peak signal level. The electrode area was 2000 μm². For a comprehensive review on CCD's and input circuits, see [10].     

A resistive-gate In0.53Ga0.47As/InPheterostructure CCD

The first InGaAs/InP charge-coupled device (CCD) is demonstrated, exhibiting a charge transfer efficiency (CTE) of 0.98 at 13 MHz and 1 GHz. Cooling the device improves the CTE to greater than 0.99 at 13-MHz clock frequency. The 0.76-eV In_0.53Ga_0.47As bandgap makes this structure applicable to direct-detection short-wavelength infrared (SWIR) imagers     

Large-signal analysis of Lo-Hi-Lo double-drift silicon IMPATT diodes at 50 GHz

Large-signal analysis of a lo-hi-lo double-drift silicon IMPATT diode at 50 GHz shows that the device is capable of output power of 1.1 W and efficiency of 20 percent for a device area of 2 × 10^-5cm²at a dc biasing current density of 12 kA/cm²and ac voltage amplitude of 12 V. It is also found that, both output power values and efficiencies decrease with increasing enhanced leakage current.     

Electrooptic effect in CdTe at 23.35 and 27.95 microns

The unlamped electrooptic coefficient r41of high-purity CdTe has been measured at 23.35 and 27.95 micros in the far infrared. The values obtained for n0³r41are 9.4 × 10^-11m/V at 23.35 µ and 8.1 × 10^-11m/V at 27.95 µ. Using previously reported values for n0, the electrooptic coefficients are found to be 5.5 × 10^-12m/V at 23.35 µ and 5.0 × 10^-12m/V at 27.95 µ. These measurements extend the region of observed electrooptic effect from 16 µ, previously obtained using GaAs, to 28 µ using CdTe.     

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.