0.35μm相移掩模模拟计算及软件设计

首先通过对０．３５μｍ接触方孔在不同相移掩模情况下硅片表面空间象光强分布的模拟计算，得出不同相移掩模情况下的最优相移参数。在几种相移掩模中，衰减型对南昌市边缘斜率最为明显，因此我们决定采用衰减型相移掩模。最后编制了相应的衫化软件，该软件能够自动生成各种相移掩模并能够模拟计算不同照明参数、不同掩模、不同数值孔径、不同离焦情况下的空间象分布，以及直接生成制作掩模时的激光直写数据。     

超厚壁聚合物光学产品多次注射-压缩成形技术研究

目的 针对聚合物材料在注射成形过程中密度变化大,在成形超厚壁光学产品时容易产生收缩、气泡等缺陷,难以满足高性能成形需求等问题,提出了一种新型多次注射-压缩成形工艺,并研究了成形次数、压缩距离等参数对厚壁光学产品成形形变和双折射的影响规律。方法 设计并制造了相应的多次注射-压缩成形模具,将超厚产品分解为若干个薄壁制件,通过连续多次注射可以实现任意厚度与分层方式的产品成形,从而实现厚壁光学产品的成形,最大成形厚度可达100 mm。在此基础上,通过实验对多次注射-压缩成形的关键参数进行了研究。结果 多次注射可改变产品的变形形式,由单次注射产品的翘曲形变转变为收缩形变,且形变值减小达70.3%。随着压缩距离的增大,产品形变呈现先减小后增大的趋势,单次注射-压缩成形产品形变值最大可减小32.7%,而多次注射-压缩产品最小收缩形变值仅为未压缩产品的1.1%。此外,与注射成形相比,压缩工艺可以减小产品的双折射,而压缩距离对双折射的影响不显著。结论 多次注射可以对单次注射成形缺陷进行补偿。通过注射-压缩成形工艺,可显著减小产品的形变,同时提高光学性能,实现超厚壁光学产品的高性能成形。     

AZ31 镁合金压痕-压平复合形变数值模拟

目的研究AZ31镁合金压痕-压平复合形变过程中工艺参数对形变区温度场、应力场、应变场、塑性变形力的影响规律。方法采用有限元模拟软件,对复合形变过程进行数值模拟研究,获得不同工艺参数条件下,温度场、应力场、应变场、塑性变形力的变化规律。结果在压痕形变过程中,随着形变温度的增大,形变区温度场的最高温度随之增大,最大塑性变形力的随之减小。在压痕形变过程中,随着模具温度的增大,形变区温度场的最高温度随之增大,最大塑性变形力随之减小。结论实验结果与数值模拟结果相吻合,说明数值模拟过程中的几何模型及相关参数设定是合理的。     

铜对孪晶诱发塑性合金组织和性能的影响

研究了铜对Fe-22.5/30 Mn-3Al-3Si TWIP钢的显微组织和力学性能的影响规律。结果表明,随着铜含量的增加,TWIP钢中奥氏体平均晶粒尺寸减小。铜含量超过0.5wt%后,TWIP钢的显微硬度明显提高。TEM观察显示TWIP钢未形变时组织中存在许多层错群和规则排列的位错列,形变后出现大量密集排列的形变孪晶和被形变孪晶分割的位错。     

微光刻相移掩模技术研究

本文系统地论述了提高光刻分辨率的相移掩模技术的基本原理、计算模拟和光刻曝光实验 ;给出了模拟和实验结果 ;研究表明 ,只有在一定的临界参数条件下 ,相移掩模才能明显地改善分辨率和工艺宽容度 ;采用无铬相移掩模得到了 0 .2 μm的清晰抗蚀剂图形 ,证明了相移掩模在提高光刻分辨率、延长光刻技术寿命以及推进光刻技术极限发展方面的优良性能     

SLM成形薄壁件尺寸偏差预测与控制研究

目的 针对选区激光熔化成形薄壁件过程中存在的变形较大、精度低等问题,通过获得最优工艺参数区间来减小薄壁件的变形。方法 利用有限元软件分析薄壁件成形过程中温度场和应力场的演化规律;建立形变量预测模型并进行试验验证,研究工艺参数对薄壁件尺寸偏差的影响,得到激光功率、扫描速度与形变量之间的关系,实现对形变量的预测和控制。结果 随着扫描层数的增加,熔池的最高温度和热影响区也随之增大,等温线越密集,温度梯度越大,最终趋于稳定;薄壁件成形过程中,出现两侧壁边缘向内倾斜、上侧边缘出现内凹的现象,薄壁件的最大应力随层数的增加而减小,最大热应力主要分布在薄壁件底层的两端;形变量随激光功率的增大而增大,随扫描速度的增大而减小,薄壁件的形变量最小约为0.02 mm;试验验证所建立的数学模型误差在10%左右,误差较小,可以对形变量进行良好的预测和控制。结论 激光功率100～200 W、扫描速度800～1 000 mm/s为最优参数区间;降低能量密度可以有效降低薄壁件形变量,提高其精度。     

现场发泡夹心墙平面内变形性能研究

为研究一种新型节能墙体--现场发泡夹心墙的平面内变形性能,制作了13片现场发泡夹心墙和1片实心墙,进行了平面内的抗震性能试验.得到了墙体滞回曲线、骨架曲线、内叶墙不同高度位移时程曲线、延性系数、能量耗散系数和刚度退化曲线等,分析了轴压比、拉接件的构造参数与布局、保温层厚度等参数变化对现场发泡夹心墙的破坏特征、破坏机制、...     

一种窄带导模共振负滤光片的设计

由于弱调制光栅可以等效为平面波导,本文从平面波导的本征方程出发,导出垂直入射时弱调制光栅共振位置的表达式.分别以单层、双层膜系导模共振光栅结构为例,研究了光栅层厚度、周期、占空比对共振波长的影响.结合光学薄膜理论设计出一种窄带导模共振负滤光片.由于导模共振对入射波参数和光栅参数都极为敏感,具有窄带效应,用来制作窄带负滤波片非常可行.     

孪晶片层结构在室温轧制过程中的微观结构演变

研究了一种具有纳米孪晶片层结构的电解沉积铜的微观结构特征及其在室温轧制形变后的微观结构演变.结果表明,电解沉积制备的纯铜样品由柱状晶组成,柱状品内含有平行于样品沉积表面的纳米量级厚度的高密度孪晶片层结构,在孪晶界上缺陷很少,为共格孪晶界.形变后,孪晶片层的微观结构特征与片层厚度密切相关.粗大的孪品片层的形变行为以全位错运动为主,而细小的孪晶片层的形变行为以肖克莱(Shockley)位错在孪晶界上的滑移为主,从而导致几个纳米厚的超细孪晶片层消失.     

相移掩模和离轴照明在ArF浸没式光刻中对工艺窗口的影响

研究了交替型相移掩模及离轴照明对65nm分辨率ArF浸没式光刻的影响,在3／4环形照明和3／4四极照明方式下,分别选用传统掩模和交替型相移掩模,研究65nm线宽的密集线条、半密集线条、孤立线条在较大的曝光系统参数范围内,对光刻工艺窗口的改善。并对在不同的照明方式、掩模结构下获得的工艺窗口进行了比较,结果表明：①在较大焦深(DOF)范围内,满足光刻性能要求可以有较大范围的曝光系统参数配置;②相时于传统照明和传统掩模,采用交替型相移掩模或者离轴照明,焦深均可提高100％-150％。     

Residual stress in piezoelectric poly(vinylidene-fluoride-co-trifluoroethylene) thin films deposited on silicon substrates

The residual stress and its evolution with time in poly(vinylidene-fluoride-co-trifluoroethylene) (P(VDF-TrFE) (72/28)) piezoelectric polymer thin films deposited on silicon wafers were investigated using the wafer curvature method. Double-side polished silicon wafers with minimized initial wafer warpage were used to replace single-side polished silicon wafers to obtain significantly improved reliability for the measurement of the low residual stress in the P(VDF-TrFE) polymer thin films. Our measurement results showed that all the P(VDF-TrFE) films possessed a tensile residual stress, and the residual stress slowly decreased with time. Our analysis further indicates that the tensile stress could arise from the thermal mismatch between the P(VDF-TrFE) film and the silicon substrate. Besides possible viscoelastic creep mechanism in thermoplastic P(VDF-TrFE) films, microcracks with widths in the range of tens of nanometers appeared to release the tensile residual stress.     

A run-to-run controller for product surface quality improvement

In semiconductor manufacturing, the surface quality of silicon wafers has a significant impact on the subsequent processes that produce devices using the wafers as a component. The surface quality of a wafer is characterised by a two-dimensional (2-D) data structure: the geometric requirement for the wafer surface is smooth and flat and the thickness should fall within certain specification limits. Therefore, both low deviation and high uniformity are desirable for control over the wafer quality. In this work, we develop a run-to-run control algorithm for improving wafer quality. Considering the unique 2-D data structure, we first construct a model that encompasses the spatial correlation of the observations on the wafer surface to link the wafer quality with the process variables, and subsequently develop a recursive algorithm to generate optimal set points for the controllable factors. More specifically, a Gaussian-Kriging model is used to characterise the spatial dependence of the thickness measures of the wafer and a recursive least square method is employed to update the estimates of the model parameters. The performance of the new controller is studied via simulation and compared with existing controllers, which demonstrates that the newly proposed controller can effectively reduce the surface variations of the silicon wafers.     

Microelectromechanical system pressure sensor integrated onto optical fiber by anodic bonding

Optical microelectromechanical system pressure sensors based on the principle of Fabry-Perot interferometry have been developed and fabricated using the technique of silicon-to-silicon anodic bonding. The pressure sensor is then integrated onto an optical fiber by a novel technique of anodic bonding without use of any adhesives. In this anodic bonding technique we use ultrathin silicon of thickness 10 microm to bond the optical fiber to the sensor head. The ultrathin silicon plays the role of a stress-reducing layer, which helps the bonding of an optical fiber to silicon having conventional wafer thickness. The pressure-sensing membrane is formed by 8 microm thick ultrathin silicon acting as a membrane, thus eliminating the need for bulk silicon etching. The pressure sensor integrated onto an optical fiber is tested for static response, and experimental results indicate degradation in the fringe visibility of the Fabry-Perot interferometer. This effect was mainly due to divergent light rays from the fiber degrading the fringe visibility. This effect is demonstrated in brief by an analytical model.     

Tantalum metallization and properties of silicon MOS structures under stress

Stresses at the surface of a silicon wafer and at the Si-SiO₂ interface were induced by the sputter deposition of tantalum films. The sputtering of tantalum produced deformation of the silicon wafers by bending, and the radius of curvature was a function of the tantalum sputtering voltage and the tantalum film thickness. The magnitude of the stress induced at the silicon surface was determined from automatic Bragg angle control measurements of the radius of curvature. The surface distribution of the strain field and its distribution in the bulk of the silicon wafer were observed by the use of X-ray transmission topography. The electrical properties of the MOS capacitor were studied as a function of the induced stress. It was found that the largest changes with induced stress occur in the values of recombination time and capture cross section, while the surface state charge density Q_ss and the surface state density N_ss are not significantly affected. Auger electron spectroscopy showed that implanted tantalum atoms diffuse through the SiO₂ and reach the silicon surface.     

自分离硅微通道的氧化

本文研究了自分离硅微通道(self lift-off silicon microchannels)的氧化问题。自分离是在特定的实验条件下,在完成电化学刻蚀后,硅微通道可以自动和衬底分离的一种新技术。研究发现,在使用传统的干氧-湿氧-干氧氧化化过程中,硅微通道出现了弯曲变形的现象。微通道越薄,其形变越大。通过使用较厚的硅微通道以及在干-湿-干氧化过程之前增加了干氧,以及先进行激光切割的步骤,改善和基本消除了弯曲变形的现象。     

Using thin film stress to produce precision, figured X-ray optics

We are studying the possibility of producing precision, aspherical mirrors for X-rays and visible light. Our study examines the use of ultrastructure processing to replace mechanical methods of material removal. The method starts with a chemically-mechanically polished, flat silicon wafer. The aim is to preserve atomic scale smoothness of the surface wafer while the wafer is bent to a desired figure. We report measurements of the mechanical properties of various stressing layers. This involves measuring the deformation of several thin silicon wafers coated with chemically vapor deposited nickel and boron films of known thickness. We have found that, under normal conditions, the film does not add to the microroughness of the substrate on either the front or the back surfaces. Film and substrate thicknesses, however, vary by as much as 10%. This is the present limit on figure accuracy. We have developed a model that describes bending of B/Si and Ni/Si structures. The model relates stress and Young's modulus to the measured thickness of the film, and the thickness and curvature of the substrate. This approach is used to measure the stress and Young's modulus for boron and nickel films. The Young's modulus E_f was 3.05 x 10¹² Pa for the boron films and 1.4 x 10¹⁰ Pa for the nickel films. From the relationship developed and verified for predicting the radii of curvature of the substrate, if may be possible to define a film thickness pattern which would provide a desired optical figure.     

标准硅片厚度测量装置的研制

利用电感测微仪的高分辨率和红宝石工作台的高灵敏度,在对传感器进行非线性修正的基础上,提出了垂直于标准硅片表面方向的点对点测量方法,研制了标准硅片厚度测量装置.整套装置适用于直径不大于305 mm标准硅片的厚度校准,对不同的直径和厚度的标准硅片,测量不确定度达到0.2μm.通过对不同厚度的标准硅片进行测量和比对,验证了装置的测量不确定度,具有结构紧凑、操作简便、准确度高、可靠性好的特点,实现了标准硅片厚度的量值溯源.     

The van der Pauw stress sensor

Piezoresistive sensors fabricated on (100) and (111) silicon surfaces are capable of measuring from four to all six components of the stress state at a point on the surface of an integrated circuit die. Such resistor-based sensors have been successfully designed and fabricated on these wafer planes and have been used successfully for measurement of die stresses in electronic packages by many research teams. In this paper, classical van der Pauw (VDP) structures, traditionally used for sheet resistance measurement, are shown to provide more than three times the sensitivity of standard resistor sensors. A single four-terminal VDP device replaces two resistor rosette elements and inherently utilizes the high-accuracy four-wire resistance measurement method. Theoretical expressions are developed for the change in resistance of the VDP device as a function of the individual stress components resolved in wafer coordinate systems on both the (100) and (111) silicon surfaces, and it is predicted theoretically that VDP devices will exhibit more than three times higher sensitivity to stress than standard resistor sensors. Design, fabrication, and experimental characterization of VDP and resistor test structures are presented for both silicon surfaces, and numerical simulation is used to help resolve discrepancies between theory and experiment. Sources of experimental error are identified, and the 3.16 times sensitivity enhancement of the VDP device is confirmed.     

Radiation thermometry of silicon wafers based on emissivity-invariant condition

An emissivity-invariant condition for a silicon wafer was determined by simulation modeling and it was confirmed experimentally. The p-polarized spectral emissivity at a wavelength of 900 nm and at temperatures over 900 K was constant at 0.83 at an angle of about 55.4° irrespective of large variations in the oxide layer thickness and the resistivity due to the different impurity doping concentrations of the silicon wafer. The expanded uncertainty, U(c) = ku(c) (k = 2), of the temperature measurement is estimated to be 4.9 K. This result is expected to significantly enhance the accuracy of radiometric temperature measurements of silicon wafers in actual manufacturing processes.     

Formation of a two-sided porous structure during electrochemical silicon etching by the Unno-Imai method

It is shown that the formation of porous silicon on the anode side of a silicon wafer by the liquid-contact method is accompanied by the appearance of a modified layer on the cathode side of the wafer. The thin modified layer has a porous structure and can attain the thickness of up to several microns. Unlike the main porous silicon layer, the modified porous layer on the cathode side is characterized by high electric conductivity. It is established that this layer also contains platinum and rhodium distributed over the whole layer thickness. Possible practical applications of the modified layer are considered.