A high-performance N-channel MOSLSI using depletion-type load elements

A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.     

A new family of low-power CT/SUP 2/L circuits

A new family of low-power logic circuits, employing a multiemitter transistor input circuit and a modified complementary p-n-p n-p-n output stage, having almost the same performance as standard TTL circuits and suitable for IC use, is reported in this correspondence.     

Technique for sensing inductor and DC output currents of PWM DC-DCconverter

The design, analysis and trade-offs of a novel method to sense the inductor and DC output currents of PWM converters are presented. By sensing and adding appropriately the currents in the transistor, rectifier and capacitors of a converter using current transformers, the waveforms of inductor and DC output currents can be reconstructed accurately while maintaining isolation. This method offers high bandwidth, clean waveform, practically zero power dissipation and simple circuit. The technique is applicable to all PWM converters in both continuous and discontinuous modes, and is most suitable for the implementation of current mode control schemes like hysteretic, PWM conductance control, and output current feedforward. This approach has been experimentally verified at a wide range of current levels, duty cycles, and switching frequencies up to 1.4 MHz     

两种晶体管饱和输出状态的比较分析

在高校的“数字电路”课程教学中,通常要对分立NPN晶体管和TTL门电路的低电平输出近饱和、饱和以及退饱和状态进行讲解,其中出现了貌似矛盾的现象。本文给出了两种情况下的比较分析,力图廓清对它们模棱两可的理解,并尝试给出了“被动饱和”与“主动饱和”两个新概念,建议了更为合理的饱和深度的定量表达式,以期对相关的教学以及教材编写起到积极的作用。     

Transistor Schottky-barrier-diode integrated logic circuit

A new high-speed low-power logic circuit using Schottky barrier diodes to avoid saturation of bipolar transistors is described. An experiment using discrete devices and a theoretical calculation show the possibility of subnanosecond logic using a saturated-type transistor logic circuit. A theoretical comparison with CML shows a 2:1 advantage in the speed-power product. The compatibility of Schottky barrier diode with monolithic silicon integrated circuit processing is shown. A prototype TTL circuit is described. Experimental results are given.     

A destructive instability in selective high-power amplifiers with bipolar transistors

An oscillation mode is described which, under certain circumstances, can be excited in selective high-power amplifiers with bipolar transistors. This instability can arise after a single saturation of the transistor and does not depend on feedback or parasitic elements. It is caused by the storage time of the transistor after a saturation. Out of the oscillation mechanism it is shown that transistor voltages and currents during this oscillation mode can be manifold the values of the normal operation. On this account, usually one or a few oscillations of this mode destroy the output transistor, either by voltage of current overload. A computation method is shown with stability charts which describe stability conditions of a given amplifier, depending on the values of the elements of the peripheral circuitry.     

Optimization-based placement algorithm for BiCMOS leaf cellgeneration

We present a transistor placement algorithm for the automatic layout synthesis of logic and interface cells comprised of a mixture of MOS and bipolar devices. Our algorithm is applicable to BiCMOS logic cells, ECL logic cells as well as TTL, CMOS and ECL compatible input/output (I/O) cells. The transistor placement problem is transformed into a layout floorplan design problem with a mixture of rigid and flexible modules. A constructive “branch-and-bound” algorithm is used to minimize the area of synthesized circuits subject to pre-placement constraints. Experimental results indicate that the algorithm can produce efficient placements under fixed-height constraints. The design space exploration mechanism can be controlled by the user so as to apportion computing resources judiciously     

Monte Carlo simulation of bipolar transistors

A new approach is proposed to investigate, the limits of validity of the conventional drift-diffusion equation analysis for modeling bipolar transistor structures containing submicrometer dimensions. The single-particle Monte Carlo method is used for the solution of the Boltzmann equation. An electron velocity overshoot of 1.8 times the static saturation velocity has been found for electrons near the base-collector junction of a silicon device. The effect of this velocity overshoot was calculated to enhance the output collector current and reduce the electron transit time by 5 percent for the device structure considered in this work.     

一种隐私保护的安全DTN发布订阅协议

容迟网络是一种新型无线网络技术，近年来与命名数据网络有着融合发展的趋势。这里以发布／订阅多播协议为原型，构造了容迟网络环境下的命名数据网络环境，探讨了该环境下的安全和隐私问题。并进一步提出了基于群签名的数据包隐私保护验证方案，以及基于哈希链的防篡改TTL网络拥塞控制方案，来抵抗泛洪攻击等恶意行为。仿真实验表明基于TTL的网络拥塞控制安全方案可以有效地控制网络中的泛洪攻击等恶意行为，而哈希链方案可以有效防止用篡改TTL的方式来变相阻塞网络。     

一种驱动MOS管工作在饱和区的硅基OLED微显示像素电路

硅基OLED微显示中为了在极小的像素面积内实现微小的OLED工作电流,其像素驱动电路的驱动MOS管一般工作在亚阈值区,存在OLED电流对驱动MOS管的阈值电压和栅源电压失配敏感、外围电路复杂等问题,如果驱动MOS管工作在饱和区则可避免这些问题,但为了获得微小的驱动电流,必须采用尺寸大的倒比MOS管,这又与极小的像素面积冲突。本文提出了一种采用脉宽调制(PWM)技术、驱动MOS管工作在饱和区的OLED微显示像素驱动电路,PWM信号减少了一帧内OLED的实际工作时间,OLED的脉冲电流变大,使驱动MOS倒比管的尺寸减小;由于PWM信号占空比小,同时实现了OLED微小的平均像素驱动电流和亮度。结果表明PWM信号占空比为3%时,实现的OLED驱动电流和像素亮度范围分别为27pA~2.635nA、2.19~225.1cd/m~2,同时采用双像素版图共用技术,在15μm×15μm的像素面积内实现了像素驱动电路的版图设计。     

Large periphery high-power AlGaN/GaN metal-oxide-semiconductorheterostructure field effect transistors on SiC with oxide-bridging

We report on AlGaN/GaN metal oxide semiconductor heterostructure field effect transistor (HFET) over SiC substrates with peripheries from 0.15 to 6 mm. These multigate devices with source interconnections were fabricated using a novel oxide-bridging approach. The saturation current was as high as 5.1 A for a 6 mm wide device with a gate leakage of 1 μA/cm² for 1.5 μm gate length in a 5 μm source-drain opening. The cutoff frequency of around 8 GHz was practically independent of the device periphery. Large-signal output rf-power as high as 2.88 W/mm was measured at 2 GHz. Both the saturation current and the rf-power scaled nearly linearly with the gate width     

分立晶体管与TTL门电路的饱和输出状态的比较分析*

在高校的《数字电路》课程教学中，通常要对分立NPN晶体管和TTL门电路的低电平输出近饱和、饱和以及退饱和状态进行讲解，其中出现了貌似矛盾的现象。本文给出了两种情况下的比较分析，力图廓清对它们模棱两可的理解，并尝试给出了“被动饱和”与“主动饱和”两个新概念，建议了更为合理的饱和深度的定量表达式，以期对相关的教学以及教材编写起到积极的作用。     

一种应用于低压CMOS差分放大器的失调取消技术

基于对CMOS差分放大器的非线性和元件失配理解的基础上,提出了一种应用于低电压CMOS差分放大器的失调取消技术.这种技术在不需要增加功耗的基础上,通过把输出端的失调电压转移到差分放大器的其他节点,从而达到减小输入参考的失调电压的目的.为了验证这种技术,设计了一个工作电压为1.8V的低失调的CMOS差分放大器.仿真结果表明,在负载晶体管的失配为20%,输入放大管的失配为10%时,利用这种失调转移技术,输入参考的失调可以减少40%.同已发表的失调取消技术相比,利用这种技术可以达到更低的功耗和更高的集成度.     

A pulsewidth-modulated inverter with parallel connected transistorsusing current-sharing reactors

A technique for parallel connection of transistors by using current-sharing reactors for the pulse-width-modulated (PWM) transistor inverter is reported. The technique not only increases current capacity, but also decreases the output harmonic contents. The output voltage waveforms of the proposed inverter have certain voltage levels during their half cycles, and thus it is anticipated that it will be difficult to analyze the output harmonics. For such waveforms, a frequency analysis approach is described, and its results are verified by experiments     

Series-parallel association of FET's for high gain and highfrequency applications

This paper presents a simple approach in the design of composite field effect transistors with low output conductance. These transistors consist of the series association of two transistors, with the transistor connected to the drain terminal wider than the transistor connected to the source terminal. It is shown that this composite transistor has the same DC characteristics as a long-channel transistor of uniform width. A composite transistor has two main advantages over its “DC equivalent” transistor of uniform width: significant area savings and a higher cutoff frequency. The main application is low-voltage, high-frequency analog circuits. The proposed technique is particularly suited for analog design in gate arrays     

Forward body-bias MOS (FBMOS) dual rail logic using an adiabaticcharging technique with sub -0.6 V operation

A novel logic family for low-voltage adiabatic logic, called forward body-bias MOS (FBMOS) dual rail logic, has been proposed. This technique uses forward body-bias effects to enable non-floating output levels during the entire data valid time without increased transistor count     

Fault diagnosis technology based on transistor behavior analysis for physical analysis

The novel method has been developed to detect accuracy fault elements in transistor level circuit, analyzing the characteristics of circuit operation influenced on leakage fault and being combined with diagnosis software, based on switching level simulation. This method is based on behavior of CMOS transistor to which applied unstable voltage produced by leakage fault. Unsettled logic brings the transistor’s operation point to saturation area with multi-impedance value and forms penetration current nets passing through it. Output value on the net is calculated with each element impedance value and miss-logic signal is spread to output terminal. An evaluation of this technology corroborates to be precise method by using the circuit in which embedded arbitrary fault portions.     

Physical mechanisms leading to deterioration of transistor life

Life tests on surface-barrier-type transistors have been conducted at various temperatures and power levels to identify and characterize the mechanisms which cause the transistor characteristics to deteriorate with time. Three mechanisms have been isolated: the formation of solution cavities in the base of the transistor, an increase in surface recombination velocity, and a decrease in surface resistance. In the normal surface-barrier transistor, the formation of solution cavities proceeds with an activation energy of about 20,000 cal. mole. This leads to an exponential dependence of life expectancy on temperature and dissipation. The formation of solution cavities is eliminated by the microalloy process, in which case the life expectancy is probably determined by the decrease in surface resistance or the increase in surface recombination velocity. The increase in surface recombination velocity causes a well-correlated decrease in current gain and grounded-base output impedance. The decrease in surface resistance produces an increase in the collector "saturation" current and may contribute to a decrease in output resistance. The formation of solution cavities brings about a decrease in punch-through voltage and grounded-emitter output impedance.     

AlGaAs/GaAs HBT model estimation through the generalizedpencil-of-function method

An efficient technique of extracting the small-signal model parameters of the heterojunction bipolar transistor (HBT) is proposed in this paper. The relation between the extrinsic and intrinsic model parameters, which can be employed to drastically reduce the search space, is studied in depth. For the first time, the HBT transistor is characterized by describing S-parameters with a set of complex exponentials using the generalized pencil-of-function method. The reliable initial values of some extrinsic elements can be determined from the set of complex exponentials. This novel approach can yield a good fit between measured and simulated S-parameters