Si晶体中Cu和Fe杂质在Frank型位错上的不同沉淀行为

本文运用电子束感应电流技术和透射电子显微镜研究了直拉Ｓｉ单晶中Ｃｕ和Ｆｅ杂质在Ｆｒａｎｋ型位错上的沉淀行为．发现尽管在Ｓｉ中Ｃｕ杂质浓度远高于Ｆｅ杂质，但Ｃｕ杂质不沉淀在Ｆｒａｎｋ型位错上，而Ｆｅ杂质会沾污Ｆｒａｎｋ型位错．研究结果表明，样品中微小Ｐｕｎｃｈｅｄ－ｏｕｔ位错的存在和Ｃｕ杂质在Ｓｉ中的重复成核机制是Ｃｕ杂质不沉淀在Ｆｒａｎｋ型位错上的主要原因．     

SIMOX材料铁杂质沾污的紫外光致荧光分析

本文用紫外光致荧光法无损检测孙同工艺参数制备ＳＩＭＯＸ材料正面和背面的铁杂质沾污程度，得出了这些样品铁杂质浓度的相对大小。     

GaN异质外延中的侧向生长技术

以GaN为代表的Ⅲ族氮化物在微电子、光电子和传感器等领域均发挥了重要作用.但是由于大尺寸的单晶GaN衬底仍无法实现,目前绝大多数氮化物材料都是通过异质外延的方式来实现,外延材料和异质衬底之间巨大的晶格失配和热失配是导致GaN外延层中位错密度较高的主要原因.侧向生长(ELOG)技术是GaN异质外延中降低位错密度的一种有效方法,总结了该项技术的特点,并对单步ELOG技术、双步ELOG技术、悬空ELOG技术以及无掩膜ELOG技术等多种技术趋势进行了总结.ELOG技术可以有效降低位错密度,但是仍需降低工艺复杂性和减少沾污.     

原位退火对Si基CdTe材料的位错抑制研究

硅与碲镉汞之间的外延碲化镉缓冲层能够减小外延过程中产生的高达10⁷ cm^-2的位错密度,高温热退火是抑制材料位错的有效方法之一。传统的离位退火技术会导致工艺不稳定和杂质污染等,而原位退火则可有效解决这些问题。利用原位退火技术对分子束外延生长的硅基碲化镉材料进行了位错抑制研究。对厚度约为9■m的碲化镉材料进行了6个周期不同温度的热循环退火,并阐释了不同退火温度对硅基碲化镉材料位错的抑制效果。采用统计位错腐蚀坑密度的方法对比了退火前后材料的位错变化。可以发现,在退火温度为520℃时,位错密度可以达到1.2×10⁶ cm^-2,比未进行退火的CdTe材料的位错密度降低了半个数量级。     

集成电路芯片的工艺诱生缺陷

调研了三条100—150mm集成电路生产线上IC芯片的工艺诱生缺陷。研究表明，这些IC生产线上存在三种影响IC成品率的主要诱生缺陷，离子注入诱生弗兰克不全位错，薄膜应力和杂质收缩应力引起的位错和隔离扩散区的位错。前二种缺陷存在于MOS电路，后一种存在于双极型电路。弗兰克不全位错起因于离子注入损伤诱生的氧化诱生层错(OISF)，薄膜应力和杂质收缩压力引起的位错和隔离扩散区的位错都与薄膜应力和高浓度替位杂质的收缩应力有关。同时，提出了减少这几类缺陷密度的工艺途径。     

用固溶强化模型计算InP中等价电子杂质对位错的钉扎力

本文根据固溶强化模型,考虑了等价电子杂质在InP单晶中的溶解度以及掺入杂质与基质原子之间共价半径之差引起的弹性失配.计算了这些杂质在InP 中对位错的钉扎力可达10~9～10~(10)达因/厘米~2,从而很好地解释了等价电子杂质降低位错密度的作用.     

半导体材料

0205855低剂量 SIMOX 圆片线缺陷的针孔的研究[刊]/郑望//功能材料与器件学报.—2001.7(4).—431～433(C)用 Secco 法、Cu-plating 法分别表征了低剂量SIMOX 圆片顶层硅线缺陷、埋层的针孔密度。结果显示,低剂量 SIMOX 圆片的顶层硅缺陷密度低,但埋层质量稍差。通过注入工艺和退火过程的进一步优化,低剂量 SIMOX 将是一种有前途的 SOI 材料制备工艺。参7     

硅外延S坑缺陷的研究

用扫描电镜、透射电镜和二次离子质谱研究了硅外延片中的Ｓ坑缺陷。在Ｓ坑缺陷中观察到一种线度比通常Ｓ坑更大的浅底坑缺陷。研究表明Ｓ坑缺陷分布在３～４μｍ深的外延表面层中，其结构为位错缠结及带有杂质沉淀的缺陷团。Ｓ坑缺陷起因于金属杂质的沾污。     

基于100mm国产SiC衬底高性能AlGaN/GaN异质结外延材料

南京电子器件研究所提出了一种"AlN表面原位图形化"技术,将AlN成核岛台阶化(图1),改善GaN缓冲层的外延生长模式,抑制GaN/AlN界面位错的生成以及纵向延伸,从而降低GaN缓冲层的穿透位错密度。另外,原位制备工艺容易实现,避免杂质引入,降低外延成本。采用该技术在100 mm国产高纯半绝缘SiC衬底上制备出1.8 μm厚高质量GaN HEMT外延材料,GaN缓冲层(002)和(102)面摇摆曲线半高宽分别达到56、147 arcsec(图2),与常规工艺相比位错密度降低80%,二维电子气室温迁移率达到2 300 cm^2/(V·s),材料结晶质量和电学特性获得显著提升。     

适合集成电路生产的SIMOX SOI

由于SIMOX SOI(氧离子注入隔离绝缘体上硅膜材料)能很好地满足当今的集成电路要求,并能同传统的集成电路制造兼容,它越来越广泛地用于集成电路(IC)的生产。本文介绍SIMOX的这些特性及其当前的应用。     

The effect of heavy metal contamination in SIMOX on radiationhardness of MOS transistors

It is shown that heavy metal contamination introduced during implantation of oxygen into silicon results in a reduction of SIMOX (separation by implanted oxygen) oxide radiation hardness. Radiation-induced back-channel leakage currents in MOS transistors processed in SIMOX films containing various levels of heavy metals, as measured by surface photovoltage (SPV), are a strong function of heavy metal concentration. It is concluded that SPV measurements of as-implanted SIMOX wafers can be used as a rapid, nondestructive quality control inspection technique to predict the radiation hardness of the SIMOX oxide prior to processing     

应用ICP-AES表征高剂量氧注入过程中的金属污染

研究了采用感应耦合等离子体原子发射光谱技术表征高剂量氧注入单晶硅制备SIMOX SOI材料过程中金属杂质污染的有效性.同时研究了采用强酸清洗、加SiO2 膜覆盖等方法对降低污染程度的效果.利用ICP技术可以对大面积或整个硅片进行采样,检测结果是一种整体的平均效果.采用强流氧注入机进行高剂量氧注入,发现金属杂质污染元素主要是Al、Ar、Fe、Ni;注入后强酸清洗样品可有效降低Al污染;6 0nm厚的二氧化硅注入保护膜可阻挡一半的上述金属污染.     

Optimizing gettering conditions for VLSI chips using simple yieldmodel

Conditions of an effective gettering procedure for VLSI processing are investigated by means of analytical simulation. The effectiveness of a gettering procedure is judged from the VLSI yield when the density of heavy metal impurities and gettering capability are varied over a wide range. It is found that the VLSI yield is seriously degraded by the negative effects of gettering, namely, wafer warpage and dislocation propagation from a gettering site region to a device area. It is seen that gettering effects are profitable in VLSI processes only when the density of heavy metal impurity to be removed is not too high     

低剂量SIMOX圆片研究

用二次离子质谱、剖面透射电镜、高分辨电镜以及化学增强腐蚀法表征了低剂量 SIMOX圆片的结构特征 .结果显示 ,选择恰当的剂量能量窗口 ,低剂量 SIMOX圆片表层 Si单晶质量好、线缺陷密度低埋层厚度均匀、埋层硅岛密度低且硅 /二氧化硅界面陡峭 .这些研究表明 ,低剂量 SIMOX圆片制备是很有前途的 SOI制备工艺     

SIMOX技术及CMOS／SIMOX器件的研究与发展

SIMOX技术是最具有发展前途的SOI技术之一。在发展薄硅层、深亚微米OMOS/SOI集成电路中,SIMOX技术占有极其重要的地位。本文综述了SIMOX基片的形成、高质量SIMOX基片的制备方法。阐述了薄硅层OMOS/SIMOX器件的工艺特点以及器件的性能特点。本文也就SIMOX技术及GMOS/SIMOX器件的研究现状及发展趋势进行了讨论。     

Practical reduction of dislocation density in SIMOX wafers

The dislocation density in the superficial silicon layers of SIMOX wafers formed under different oxygen implantation conditions has been investigated using a Secco etching technique. An extremely low dislocation density in the order of 10/sup 2/ cm/sup -2/ has been obtained for waters implanted at 180 keV with a dose of 0.4*10/sup 18/ and doses ranging from 0.9 to 1.2*10/sup 18/O/sup +//cm/sup 2/ at a wafer temperature of 550 degrees C followed by post-implant anneal at temperatures higher than 1300 degrees C. The buried oxide layers of the SIMOX wafers have breakdown voltages higher than 40 V.<>     

CdZnTe晶片的红外透过率研究

测试了多个性能各异的Cd0.9Zn0.1Te晶片的红外透过率。研究表明,红外透过率与晶片的性能有着密切的联系,即红外透过率的大小及红外透过率图谱的形状可反映晶片的成分分布、位错密度以及杂质含量的情况。从晶片对红外光的吸收机理出发,对这些联系进行了详细的分析。     

Conductivity-type conversion in multiple-implant/multiple-annealSOI

Results of an investigation of the electrical properties of superficial silicon and epitaxial capping layers grown on multiple-implant/anneal SIMOX and zone melt recrystallization substrates are presented. An unexpected SIMOX conductivity type change (from n to p) was observed in the SIMOX superficial layer, as well as in subsequently grown epi-layers. It is believed that the conductivity-type change is related to the presence of a process-induced acceptor impurity or an impurity (oxygen)-vacancy complex     

Dislocation scattering in n-GaN

The scattering of carriers due to dislocations is studied. Unlike semiconductors such as Si or GaAs, the major scattering mechanism for undoped or lightly doped samples is dislocation scattering instead of ionized impurity scattering. It was found that for GaN samples in the dislocation scattering region, the mobility is a function of the dislocation density and free carrier concentration, via a relationship. Temperature-variation mobility plots also indicate that a T^3/2 dependence component is present, which is also attributed to dislocation scattering.     

Fabrication of SiGe optical waveguides using VLSI processingtechniques

The fabrication of rib waveguides in SiGe using the local oxidation of silicon (LOCOS) was investigated. Samples consisted of strained Si_.97Ge_.03 or Si_.94Ge_.06 waveguiding layers with silicon cladding layers. The structural stability of these strained layers during thermal cycling up to 1050°C was examined using X-ray rocking curve analysis, scanning electron microscopy, and Nomarski microscopy of etched samples. Since single SiGe layers sufficiently thick to support optical waveguiding are typically above the equilibrium critical thickness, dislocation formation during high-temperature processing is unavoidable. This work concentrated on minimizing these dislocations. It was found that the dislocation density induced by the processing can be minimized by using a strain-compensating mask layer as a barrier to oxidation. For a specified thermal oxide layer thickness, higher oxidation temperatures were found to minimize the dislocation density relative to oxidation at temperatures closer to the metastable limit. Furthermore, the large birefringence found in all strained-layer SiGe waveguides is significantly reduced after LOGOS processing. These effects were used to fabricate the first reported optical waveguides and photonic devices in SiGe using standard VLSI-type processing. The device is a 1.3/1.55-μm duplexer with wavelength isolation of roughly 10 dB