Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance–inductance–capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.      

Comprehensive Broad-Band Electromagnetic Modeling of On-Chip Interconnects With a Surface Discretization-Based Generalized PEEC Model

A surface integral equation formalism is proposed for broad-band electromagnetic modeling of on-chip signal and power distribution networks. The discrete model is developed in the spirit of the partial element equivalent circuit (PEEC) model, which is extended with several attributes that lead to enhanced modeling versatility, modeling accuracy, and numerical solution robustness from dc to multigigahertz frequencies. Instead of the volumetric discretization model, which has dominated the PEEC-based schemes for handling the tall and slim cross sections of the on-chip wiring, the proposed model relies on a computationally more efficient conductor surface discretization. Key to the effectiveness and accuracy of the proposed surface discretization is the definition of a frequency- and position-dependent impedance quantity on the conductor surface. Its numerical computation over the frequency bandwidth of interest is expedited through the implementation of a complex frequency-hopping algorithm. The resulting effective surface impedance is combined with a mixed triangular/rectangular meshing of the conducting surfaces for the approximation of the surface electric current and charge densities. A systematic strategy for the identification of loops in the resulting discrete model is used to ensure a numerically stable mesh analysis-based PEEC formulation for on-chip signal and power distribution modeling with electromagnetic accuracy from dc to multigigahertz frequencies.     

开关电源噪声的产生与抑制

近年来,电磁干扰问题越来越成为电子产品的一个严重问题,电磁兼容技术日益成为许多技术人员重视的技术。开关电源是电子系统中的一种主要的干扰源之一,同时它的电磁兼容问题也是较难解决的。针对此分析了开关电源工作时噪声产生的原因,噪声对其它电子设备产生干扰的途径,并从电路设计、结构工艺两个方面提出了抑制噪声干扰的措施。     

互连线串扰耦合噪声的ABCD矩阵模型

高频互连线间的相互耦合和相互感应是产生串扰的一个重要因素。已有文献利用二端口网络ABCD矩阵从理论上求出了耦合互连线阶跃响应,但该方法对互感描述不准确,导致计算复杂,且对串扰耦合噪声的估计不够准确。该文根据互感的基本定义,修改了原模型中互感的表示方法,提出了一个新的ABCD矩阵级联模型,对LTCC工艺互连线的串扰耦合噪声进行分析,并将得到的ABCD模型分析结果与ADS软件的仿真结果对比,验证了改进的ABCD模型的准确性。     

Ultra-Wideband Mitigation of Simultaneous Switching Noise Using Novel Planar Electromagnetic Bandgap Structures

A novel design of power/ground plane with planar electromagnetic bandgap (EBG) structures for suppressing simultaneous switching noise (SSN) is presented. The novel design is based on using meander lines to increase the effective inductance of EBG patches. A super cell EBG structure, comprising two different topologies on the same board, is proposed to extend the lower edge of the band. Both novel designs proposed here are validated experimentally. A$-$28dB suppression bandwidth starting at 250MHz and extending to 12GHz and beyond is achieved.     

一种基于0.18μm的同步开关输出噪声模型和仿真方法

0．18μm下,同步开关输出噪声是影响信号完整性的主要噪声之一,较大的噪声有可能导致数字系统中元件的误动。本文首先简要介绍了同步开关输出噪声的产生和特点,然后给出了一种建立仿真模型和仿真的方法,这种方法快速简便而且结果精确。最后根据仿真的结果得到了一些减小同步开关输出噪声的方案。     

开关电源传导性电磁干扰共模噪声的研究

为了研究电磁干扰（EMI）噪声源的影响,实现对开关电源EMI参数的控制问题,文章基于PSPICE仿真软件,对各种常用结构的开关电路进行了分析,得出了一组开关电源电路引发传导性EMI的仿真实验数据及有关结论.仿真研究表明,当缓冲电路采用MUR190二极管、输入RC控制电路的参数设置为R=1kΩ,C=4nF时,所产生的共模噪声达到最小.     

电磁带隙结构在同步开关噪声抑制中的应用分析

随着数字电路的噪声容限和时序容限不断减小,电源地平面上的同步开关噪声(SSN)成为高速设计的主要瓶颈之一.而现有抑制SSN的方法存在各自的不足,因而提出采用电磁带隙结构(EBG)设计来抑制SSN,软件仿真证明该方法是有效的.基于对多种不同结构EBG的研究,给出了EBG的设计思路和最新发展趋势,为今后的实际应用研究提供一定的参考与指导.     

Novel Planar Electromagnetic Bandgap Structures for Mitigation of Switching Noise and EMI Reduction in High-Speed Circuits

Planar electromagnetic bandgap (EBG) structures with novel meandered lines and super cell configuration are proposed for mitigating simultaneous switching noise propagation in high-speed printed circuit boards. An ultrawide bandgap extending from 250 MHz to 12 GHz and beyond is demonstrated by both simulation and measurement, and a good agreement is observed. These perforated EBG-based power planes may cause spurious and unwanted radiation. In this paper, leakage radiation through these imperfect planes is carefully investigated. It is found that the leakage field from these planar EBG structures is highly concentrated around the feed point, and the field intensity is attenuated dramatically when passing across several periods of patches. A novel concept of using these EBG structures for electromagnetic interference reduction is also introduced. Finally, the impact of power plane with EBG-patterned structures on signal integrity is studied.     

Coupling Effect of On-Chip Inductor With Variable Metal Width

This study proposes a proper layout of on-chip inductors to diminish the coupling effect in silicon-based technology. Keeping self inductance constant, the mutual inductance is measured to characterize coupling effect in three test keys. A layout with variable metal width of inductor is found to alleviate mutual inductance. Experiment results demonstrate the mutual inductance decreases 33.5% compared with standard layout. This information will be helpful in implementation of more than one inductor into radio frequency integrated circuits (RFICs).     

High Speed On-Chip Signal Generation for Debug and Diagnosis

This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma–delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4?GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-for-test (DFT), or built-in self-test (BIST).     

Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed     

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST

In the context of analog BIST for ADC, this paper presents two structures for the internal generation of a linear signal used with the histogram-based test technique. All of these structures use wide-swing current mirrors and an original adaptive system to make the generators less sensitive to process variations. The first structure allows us to generate high quality ramp signal. In a second step, a very high accuracy triangle-wave signal generator is presented in order to improve the equivalent linearity of the generated analog test signal.     

Modeling and Characterization of On-Chip Transformers for Silicon RFIC

A broadband and scalable lumped-element model for silicon on-chip transformers is presented. Model elements are driven from layout and process technology specifications. We provide simple and accurate expressions for evaluating the self inductance and the mutual coupling coefficient. The effects of various layout parameters, including transformer area, number of turns, and turns ratio, on transformer electrical response have been investigated. Model accuracy is demonstrated by comparing simulated and measured S-parameters, minimum insertion loss, quality factor, coils inductance, and magnetic coupling of several transformers with a wide range of configurations     

砷化镓衬底上螺旋电感的建模和分析

针对砷化镓(GaAs)衬底上螺旋电感提出了一种改进形式的集总参数等效电路模型,该等效电路模型能很好地表征螺旋电感的高频效应.同时,应用电磁场全波分析方法对螺旋电感进行仿真,并分析各参数对电感性能的影响.从得到的散射参数中提取出有效电感、Q值和自谐振频率.基于参数优化方法提取等效电路模型中各元件值,并利用曲线拟合技术给出其相应的闭合表达式.这些表达式可用于射频和微波集成电路的设计,从而提高电路设计的性能和效率.     

高速印刷电路板中电磁带隙结构的同步开关噪声抑制和传输特性分析

该文从频域和时域两方面对一种正六边形贴片的电磁带隙(EBG)结构进行了特性分析和研究。利用等效电路理论分析和研究了贴片边长、贴片间距和过孔半径对该结构的带隙和传输特性的各自不同的影响,得到并验证了准确估算不同贴片边长带隙的上、下限频率和带宽的数学表达式。研究表明可以通过贴片间距来改变带宽,但不影响带隙左侧特性,过孔半径的缩小会导致带隙左移并变窄。最终分析了以EBG结构为返回路径的信号线的时域特性,实验证明EBG结构的周期越小,信号的传输质量越差。     

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

This paper presents novel methods for modeling and analysis of on-chip Single and H-tree distributed resistance inductance capacitance interconnects. The matrix pade-type approximation and scaling and squaring methods are employed for the numerical estimation of delay in single interconnect, and H-tree interconnects. The proposed models, which are based on these methods, provide rational function approximation for obtaining a passive interconnect model. Multiple single input single output model approximated transfer functions are developed for H-tree interconnects structure. With the equivalent reduced order lossy interconnect transfer functions, finite ramp responses are obtained, and line delay is estimated for various line lengths, input ramp rise times, source resistances, parasitic capacitances and load capacitances. In order to demonstrate the accuracy of proposed models, the estimated 50 % delay values are compared with the standard HSPICE W-element model and are found to be in good agreement. The proposed models worst case 50 % delay errors of single interconnect are 0.27 and 0.24 % respectively, while the worst case 50 % delay errors of H-tree structure are 5.73 and 3.94 % respectively.     

下一代网络与光交换

文章简述了用于下一代网络的交换技术,重点介绍了光交换技术,包括光分组交换、光突发交换与多协议波长交换.     

Design, Implementation, and Testing of Miniaturized Electromagnetic Bandgap Structures for Broadband Switching Noise Mitigation in High-Speed PCBs

In recent years, advances in CMOS technology, resulted in devices with higher switching speeds, lower power supply voltages, and higher package densities. Lowering the power supply voltages and hence the power consumption of a single transistor, has been possible due to the fact that these new technologies are able to provide smaller and faster transistors with lower threshold levels. The benefits associated with lowering the threshold levels of the transistors used in a given device comes at a high-price, specifically the decrease of immunity of such device to noise and fluctuations of the power supply voltages. This paper covers the concept of embedding electromagnetic bandgap (EBG) structures in conventional power distribution networks in order to increase the immunity of the circuits that feed from such networks to noise and voltage fluctuations. Underlying theories of embedded EBG (EEBG) structures and design methodologies are presented. Finally, in order to provide immunity to high-bandwidth noise, voltage fluctuations and radiation, new EEBG configurations, topologies and miniaturized structures with ultra wide-bandwidth are introduced and their efficacy is demonstrated