Comprehensive study of drain breakdown in MOSFETs

MOSFET breakdown voltage is strongly affected by the measurement conditions and the device layout. C/sub DB/,C/sub GD/,R/sub sub/, and R/sub gate/ must be extracted in order to predict the device trigger voltage under subthreshold, non-dc conditions. Substrate resistance is modeled with a simple, semi-empirical equation.     

MOSFET drain breakdown voltage

The grounded-gate or gate-assisted drain breakdown voltage of n-channel MOSFET's has been characterized for wide ranges of oxide thickness and substrate doping concentration. Two distinct regimes, one being channel-doping limited and the other being oxide-thickness limited, have been identified. We propose that these two regimes reflect two possible locations of breakdown-at the n+-p junction and in the deep-depletion layer in the n+ drain. They can be separated by their different breakdown voltage dependences on Vgand require different approaches to process improvement.     

DC pulse hot-carrier-stress effects on gate-induced drain leakagecurrent in n-channel MOSFETs

The DC pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in nMOSFETs in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate DC pulse stress parameters in GIDL which include frequency, rise/fall time, and stressing pulse amplitude. The contributions of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC pulse hot-carrier-stress reliability analysis under circuit operation     

Improved breakdown for SOI MOSFETs fabricated in electron-beamrecrystallized polysilicon

The breakdown mechanism for SOI (silicon-on-insulator) n-type MOSFETs is discussed. It is proposed that by reducing the channel lateral electric field at the drain that breakdown can be increased. A two-dimensional finite-element modeling program was used to design a treble diffused drain-sources (TDD) implant profile which would increase the breakdown voltage. The modeling showed that a linearly graded structure would lower the electric field in the channel and would subsequently increase drain-source breakdown voltage by over 20%. Transistors fabricated in e-beam recrystallized material verified these predictions     

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation.     

Total dose response studies of n-channel SOI MOSFETs for low power CMOS circuits

Key building blocks – simple ternary inverter, positive ternary inverter and negative ternary inverter have been designed for operation at a low voltage – ±1 V in 2 μm, n-well standard CMOS process and simulated in SPICE3 for use in the design of ternary logic circuits. The back-gate bias method has been used in conjunction with the width/channel (W/L) ratio of MOSFETs to generate the desired dc voltage transfer characteristics and transition region adjustment around midway between high and low logic levels.     

Safety drain voltage avoiding avalanche breakdown in MOSFET

It has been found that the avalanche breakdown voltage of MOSFET is independent of substrate bias and increases linearly with gate voltage in an operation regime. Applying this body-effect independency of breakdown, we obtain a maximum safety drain bias, below which avalanche breakdown is completely avoided. This safety drain voltage can be expressed in an empirical form ofgL_{eff}^{nu}where Leffis the effective channel length andgand ν are coefficients, dependent upon device architecture.     

Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs

The subthreshold swing and threshold voltage characteristics of multiple-gate SOI transistors have been numerically simulated. These devices behave like cylindrical, surrounding gate devices, with the exception of the corner inversion effect. The corner inversion effect is, however, shown to be negligible if the devices are fully depleted devices or if the gate insulator thickness is small enough.     

Back gate effects on threshold voltage sensitivity to SOI thicknessin fully-depleted SOI MOSFETs

The dependence of threshold voltage on silicon-on-insulator (SOI) thickness is studied on fully-depleted SOI MOSFETs, and, for this purpose, back-gate oxide thickness and back gate voltage are varied. When the back gate oxide is thinner than the critical thickness dependent on the back gate voltage, the threshold voltage has a minimum in cases where the SOI film thickness is decreased, because of capacitive coupling between the SOI layer and the back gate. This fact suggests that threshold voltage fluctuations due to SOI thickness variations are reduced by controlling the back gate voltage and thinning the back gate oxide     

Modeling of drain current overshoot and recombination lifetimeextraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms     

Threshold voltage instability at low temperatures in partiallydepleted thin-film SOI MOSFETs

A threshold voltage instability phenomenon at low temperatures in partially depleted thin-film silicon-on-insulator (SOI) SIMOX (separation by implantation of oxygen) MOSFETs is reported. This phenomenon was investigated under normal MOSFET operating conditions for temperatures ranging from 300 K down to 10 K, with both the magnitude and duration of the instability observed to be strongly dependent on temperature. Threshold voltage shifts as small as 0 V at room temperature and as large as 0.29 V at 10 K are reported. The duration of the instability ranged in the tens of minutes and was observed to increase as the temperature was decreased     

Measurement and modeling of the sidewall threshold voltage ofmesa-isolated SOI MOSFETs

Five-terminal silicon-on-insulator (SOI) MOSFETs have been characterized to determine the threshold voltage at the front, back, and sidewall as a function of the body bias. The threshold voltage shift with the body bias at the front and back interfaces can be explained by the standard bulk body effect equation. However, the threshold voltage shift at the sidewall is smaller than predicted by this equation and saturates at large body biases. This anomalous behavior is explained by two-dimensional charge sharing between the sidewall and the front and back interfaces. An analytical model that accounts for this charge sharing by a simple trapezoidal approximation of the depletion regions and correctly predicts the sidewall threshold voltage shift and its saturation is discussed. The model makes it possible to measure the sidewall threshold even when it is larger than the front threshold voltage     

Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs

A new type of abnormal drain current (ADC) effect in fully depleted (FD) silicon-on-insulator (SOI) MOSFETs is reported. It is found that the drain current becomes abnormally large for specific front- and back-gate voltages. The drain current exhibits a transient effect due to the floating body behavior and no longer follows the conventional interface coupling theory for these specific front- and back-gate bias conditions. It is shown that the ADC can be generated by the combination of gate-induced drain leakage, transient effects, and parasitic bipolar transistor action in FD SOI MOSFETs.     

Analysis of conduction in fully depleted SOI MOSFETs

The conduction characteristics of fully depleted SOI MOSFETs studied by theoretical analysis and computer simulation are discussed. In these devices the ideal inverse subthreshold slope of 59.6 mV/decade is obtained if the interface-state capacitances are much smaller than the gate-oxide and silicon-film capacitances. For above-threshold conduction, with decreasing silicon film thickness the inversion charges penetrate more deeply into the film and the transconductance increases because of the decreasing fraction of surface conduction     

Hot-hole-induced degradation in depletion-mode n-channel MOSFETs

Injection and trapping of hot holes was studied in n-channel depletion-mode MOSFETs and compared to that in enhancement devices. The rate of device degradation was found to decrease with increasing channel doping. A model is proposed explaining this behaviour from the current transport in the buried channel and from the effect of the channel doping level on the field near the drain.     

Multi-gate SOI MOSFETs

This paper describes the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, Π-gate, Ω-gate and gate-all-around) structures. Increasing the “effective number of gates” improves the electrostatic control of the channel by the gate and, hence, reduces short-channel effects. Due to the very small dimensions of the devices, one-and two-dimensional confinement effects are observed, which results in the need of developing quantum modeling tools for accurate prediction of the electrical characteristics of the devices.     

Hot-electron degradation of n-channel polysilicon MOSFETs

The stability of the hydrogen passivation in hydrogenated n-channel polysilicon MOSFETs has been studied under thermal stress and hot-electron stress at elevated temperatures. Although the hydrogen passivation is stable at 150°C, channel hot-electron stress at high temperatures appears to create additional grain boundary traps, presumably by breaking the Si-H bonds at the grain boundaries. This mechanism is in addition to the creation of acceptor-type fast interface states that occur in bulk MOSFETs     

Comparison of drain structures in n-channel MOSFET's

Practical limitations in channel lengths for n-channel MOSFET'S under 5-V operation are discussed for conventional arsenic-drain, phosphorus-drain, phosphorus-arsenic double diffused drain (DDD), and lightly doped drain (LDD) structures. Process parameter dependence of device characteristics and optimal process conditions are also evaluated for each drain structure. It is clarified that the minimum usable channel length is about 0.7-µm, which is realized by the DDD and LDD devices. In these devices, the hot-carrier-induced device degradation is no longer a major restriction on minimum channel length, but the short-channel effect and the parasitic bipolar breakdown are dominant restrictions. The phosphorus drain with a shallow junction formed by rapid thermal annealing can expand the arsenic drain limitation.     

Elimination of bipolar induced drain breakdown and singletransistor latch in submicron PD SOI MOSFET

For the first time, we report the combined application of a SiGe source and a delta-doped p⁺ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications     

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.