Figures of merit to characterize the importance of on-chipinductance

A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-μm IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.     

Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis

Interconnect resistance and inductance shield part of the load capacitance, resulting in a faster voltage transition at the output of the driver. Ignoring this shielding effect may induce significant error when estimating short-circuit power. In order to capture this shielding effect, an effective capacitance of a distributed RLC load is presented for accurately estimating the short-circuit power. The proposed method has been verified with Cadence Spectre simulations. The average error of the short-circuit power obtained with the effective capacitance is less than 7% for the example circuits as compared with an RLC model. This effective capacitance can be used in look-up tables or in empirical -factor expressions to estimate short-circuit power.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of $≪$ 5.3% at each stage and $≪$ 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 ${rm mu}hbox{m}$ ) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of $V_{{rm dd}}=1.2 hbox{V}$ and 4.8% at $V_{{rm dd}}=0.3 hbox{V}$ .      

A standby current limited performance figure of merit for deepsub-micron CMOS

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM_max. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM_max technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM_max methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM_max. The value of gate length at which FOM_max occurs decreases with decreasing supply voltage. FOM_max analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm     

Power estimation techniques for FPGAs

The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.     

Modelling of the shoot-through phenomenon introduced by the next generation IGBT in inverter applications

The shoot-through phenomenon has not been fully discussed for high-power inverters with IGBTs. This is because a negative gate voltage is applied to IGBTs during off states. Recently, attention is paid to an improved gate driver with only a positive gate voltage in order to meet demands for simplification, integration, and reduction in power consumption as well as in cost of the gate driver. Moreover, the threshold voltage of the next-generation IGBT will decrease with microfabrication techniques of the gate structure. This will make the shoot-through phenomenon severer and degrade the inverter reliability with the next-generation IGBTs. The influence of the parasitic parameters in both the IGBT and circuit on the shoot-through mechanism has not been investigated so far.This paper clarifies the shoot-through mechanism and investigates the impact of the next generation IGBTs on the inverter reliability. The influence of the internal capacitance of IGBT including stray inductance on inverter reliability is experimentally confirmed.     

Characterization of power electronics system interconnectparasitics using time domain reflectometry

The significance of interconnect parasitics of power electronics systems is their effects on power converters' electromagnetic interference (EMI)-related performances, such as voltage/current spikes, dv/dt, di/dt, conducted/radiated EMI noise, etc. In this paper, a time domain reflectometry (TDR) measurement-based modeling technique is described for characterizing interconnect parasitics in switching power converters. Experiments are conducted on power components of a prototype high-power inverter, including insulated gate bipolar transistor (IGBT) modules, busbar and bulk capacitors. It is shown that the interconnect inductance of the IGBT module can be extracted completely using TDR. It is also shown that the busbar equivalent circuit can be modeled as transmission line segments or L-C filter sections, and the bulk capacitor contains a significant equivalent series interconnect inductance     

GaAs/AlGaAs and InGaAs/AlGaAs MODFET inverter simulations

Although MODFET's have exhibited the fastest switching speed for any digital circuit technology, there is as yet no clear consensus on optimal inverter design rules. We therefore have developed a comprehensive MODFET device model that accurately accounts for such high gate bias effects as transconductance degradation and increased gate capacitance. The device model, which agrees with experimental devices fabricated in this laboratory, is used in the simulation of direct-coupled FET logic (DCFL) inverters with saturated resistor loads. Based on simulation results, the importance of large driver threshold voltage not only for small propagation delay times but for wide logic swings and noise margins is demonstrated. Furthermore, minimum delay times are found to occur at small supply voltages as seen experimentally. Both of these results are attributed to the reduction of detrimental high gate bias effects. The major effect of reducing the gate length on delay time is to decrease the load capacitance of the gate. Using 0.25-µm gates, delay times of 5 and 3.6 ps at 300 and 77 K, respectively, are predicted. Finally, the recently introduced In-GaAs/AlGaAs MODFET's are shown to have switching speeds superior to those of conventional GaAs/AlGaAs MODFET's.     

Compact distributed RLC interconnect models. I. Single linetransient, time delay, and overshoot expressions

Novel compact expressions that describe the transient response of a high-speed distributed resistance, inductance, and capacitance (RLC) interconnect are rigorously derived with on-chip global interconnect boundary conditions. Simplified expressions enable physical insight and accurate estimation of transient response, time delay, and overshoot for high-speed global interconnects with the inclusion of inductance     

A multilevel parasitic interconnect capacitance modeling andextraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays     

应用于变化条件下延时分析的反相器模型

 本文提出了一个考虑衬底耦合效应的门延迟模型.该模型在考虑衬底耦合效应下转换CMOS反相器的延迟为等效电阻和电容(RC)网络延迟.考虑工艺参数扰动和衬底耦合效应对门延时的影响,建立基于工艺扰动的简单开关电容门延迟模型,结合随机配置法和多项式的混沌展开法分析门延时.利用数值计算方法对本模型和分析方法进行验证,结果表明与HSPICE精确模型仿真结果的相对误差小于2％,证明本模型和分析方法的有效性.     

High-speed and low-power interconnect technology forsub-quarter-micron ASIC's

The optimum interconnect structure for high-speed and low-power sub-quarter-micron Application Specified Integrated Circuits (ASIC's) is investigated. High-speed and low-power scaling rules for the interconnect structures are extracted statistically from the wiring data in actual ASIC's. Adopting the scaling rule for a 0.25-μm ASIC enables us to reduce the gate delay by 23% and the gate power by 31% compared to conventional (horizontal only) scaling rule. A low-dielectric-constant interlayer insulator further reduces both the gate delay and power by reducing wiring capacitance. A 0.25-μm interconnect structure was fabricated by adopting the “high-speed and low-power interconnect scaling rule” and using organic spin-on-glass (SOG) as a low-dielectric-constant interlayer insulator. According to equivalent-circuit calculation using the measured interconnect parameters, the gate delay was reduced by 39% and the gate power was reduced by 47% compared to a conventional interconnect structure     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

Design for velocity saturated, short-channel CMOS drivers withsimultaneous switching noise and switching time considerations

Design guidelines for velocity-saturated, short-channel CMOS drivers are presented in this paper based on approximating the package inductance by an effective, lumped, power-supply bus parasitic inductance. A worst-case maximum simultaneous switching noise V_GM and gate propagation delay time t_D,1/2 are treated as performance constraints for which driver design tradeoffs between driver geometry, the maximum number of simultaneously switched drivers, and the effective inductance are obtained. For typical loading conditions, design examples based on the proposed guidelines are shown by SPICE simulations using the MOS3 model to agree with both design goals within 10%