Single flux quantum one-decimal-digit RNS adder

Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm². Chips were fabricated at HYPRES, Inc. using 1 kA/cm² low-T_c Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.     

Self-heating and destruction of high-voltage 4H-SiC rectifier diodes under a single short current surge pulse

Self-heating of high-voltage (6 kV class) 4H-SiC rectifier p⁺–n–n⁺ diodes under the action of a single 20 μs forward current surge pulse has been studied experimentally up to current densities j ≈ 100 kA/cm². The diode parameters are stable after a single surge pulse with current density j ≈ 60 kА/cm², although the estimated temperature of the diode at the end of this pulse is ～1650 K. After several pulses of this amplitude or after subjecting the diode to pulses with higher current density, the diode degrades. The degradation is manifested in an irreversible decrease of the differential resistance of the diode under a high forward bias. Even a single 20 μs pulse with peak current density j ≈ 100 kA/cm² leads to total destruction of the device.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

High power 4H–SiC pin diodes (10 kV class) with record high carrier lifetime

The hole lifetime τ_p in the n-base and isothermal (pulse) current–voltage characteristics have been measured in 4H–SiC diodes with a 10 kV blocking voltage (100 μm base width). The τ_p value found from open circuit voltage decay (OCVD) measurements is 3.7 μs at room temperature. To the best of the authors’ knowledge, the above value of τ_p is the highest reported for 4H–SiC. The forward voltage drops V_F are 3.44 V at current density j = 100 A/cm² and 5.45 V at j = 1000 A/cm². A very deep modulation of the blocking base by injected non-equilibrium carriers has been demonstrated. Calculations in term of a simple semi-analytical model describe well the experimental results obtained.     

Development of highly conducting n-type micro-crystalline silicon oxide thin film and its application in high efficiency amorphous silicon solar cell

Wide band gap and highly conducting n-type nano-crystalline silicon film can have multiple roles in thin film solar cell. We prepared phosphorus doped micro-crystalline silicon oxide films (n-μc-SiO:H) of varying crystalline volume fraction (X_c) and applied some of the selected films in device fabrication, so that it plays the roles of n-layer and back reflector in p-i-n type solar cells. It is generally understood that a higher hydrogen dilution is needed to prepare micro-crystalline silicon, but in case of the n-μc-SiO:H an optimized hydrogen dilution was found suitable for higher X_c. Observed X_c of these films mostly decreased with increased plasma power (for pressure<2.0 Torr), increased gas pressure, flow rate of oxygen source gas and flow rates of PH₃>0.08 sccm. In order to determine deposition conditions for optimized opto-electronic and structural characteristics of the n-μc-SiO:H film, the gas flow rates, plasma power, deposition pressure and substrate temperature were varied. In these films, the X_c, dark conductivity (σ_d) and activation energy (E_a) remained within the range of 0–50%, 3.5×10⁻¹⁰ S/cm to 9.1 S/cm and 0.71 eV to 0.02 eV, respectively. Low power (30 W) and optimized flow rates of H₂ (500 sccm), CO₂ (5 sccm), PH₃ (0.08 sccm) showed the best properties of the n-μc-SiO:H layers and an improved performance of a solar cell. The photovoltaic parameters of one of the cells were as follows, open circuit voltage (V_oc), short circuit current density (J_sc), fill-factor (FF), and photovoltaic conversion efficiency (η) were 950 mV, 15 mA/cm², 64.5% and 9.2% respectively.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

Biaxially aligned YBCO film tapes fabricated by all pulsed laser deposition

Biaxially aligned yttria-stabilized zirconia (YSZ) films on Ni-based alloy substrates were realized with high deposition rate of 0.5 μm min⁻¹ by the inclined substrate deposition (ISD) technique without ion beam assistance. The microstructure of YSZ was examined to study the growth mechanism of biaxial alignment by ISD. Columnar structures toward the plasma plume suggested a self-shadowing effect in the ISD process. To raise I_c values, YBCO thickness was increased up to 5 μm. Thick YBCO films with high J_c values were realized on the ISD-grown YSZ. Long YBCO tapes with biaxial alignment were successfully fabricated using continuous pulsed laser deposition and a high I_c value of 37.0 A (77.3 K, 0 T) at a 75 cm voltage tap spacing was achieved.     

High-performance C60 and picene thin film field-effect transistors with conducting polymer electrodes in bottom contact structure

C₆₀ and picene thin film field-effect transistors (FETs) in bottom contact structure have been fabricated with poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) (PEDOT:PSS) electrodes for a realization of mechanical flexible organic FETs. The C₆₀ thin film FETs showed n-channel enhancement-type characteristics with the field-effect mobility μ value of 0.41 cm² V^?1 s^?1, while the picene thin film FET showed p-channel enhancement-type characteristics with the μ of 0.61 cm² V^?1 s^?1. The μ values recorded for C₆₀ and picene thin film FETs are comparable to those for C₆₀ and picene thin film FETs with Au electrodes.     

Contact resistivity of amorphous and crystalline GeCu2Te3 to W electrode for phase change random access memory

We have investigated the contact resistivity of GeCu₂Te₃ (GCT) phase change material to a W electrode using the circular transfer length method (CTLM). The contact resistivity ρ_c of as-deposited amorphous GCT to W was 3.9×10⁻² Ω cm². The value of ρ_c drastically decreased upon crystallization and crystalline GCT that annealed at 300 °C showed a ρ_c of 4.8×10⁻⁶ Ω cm². The ρ_c contrast between amorphous (as-deposited) and crystalline (annealed at 300 °C) states was larger in GCT than in conventional Ge₂Sb₂Te₅ (GST). Consequently, it was suggested from a calculation based on a simple vertical structure memory cell model that a GCT memory cell shows a four times larger resistance contrast than a GST memory cell.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

Melt texturing of YBCO for high current applications

In recent years significant progress has been made in J_c enhancement in high T_c superconductors using melt texturing techniques. Among the many melt texturing methods and modifications, seeding and directional solidification techniques offer extensive control over the location of the growth front and the growth direction over long distances during melt texturing which makes these techniques most attractive from the standpoint of long conductor fabrication. These processes have the capability of producing J_cs of about 45 000 A cm⁻² across single domains of YBCO. A novel variant of the conventional melt texturing process called the liquid phase removal method provides a means to improve the grain boundary coupling in melt textured bulk polycrystalline HTS. Grain boundaries in samples processed by this technique with misorientation angles as high as 54° have demonstrated J_cs as high as 18 000 A cm⁻². Recent developments in texturing of RE-123 compounds (Nd and Yb) at high growth rates give promise for considerable reduction in processing times in directional solidification. Texturing has been observed even in samples processed at rates as high as 100 mm h⁻¹. With these advances in melt texturing methods, utilization of bulk HTS in practical applications such as high capacity current leads etc., appears to be a distinct possibility of the near future.     

Solution processable poly(2,5-dialkyl-2,5-dihydro-3,6-di-2-thienyl-pyrrolo[3,4-c]pyrrole-1,4-dione) for ambipolar organic thin film transistors

Solution processable diketopyrrolopyrrole (DPP)-bithiophene polymers (PDBT) with long branched alkyl side chains on the DPP unit are synthesized. These polymers have favourable highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) energy levels for the injection and transport of both holes and electrons. Organic thin film transistors (OTFTs) using these polymers as semiconductors and gold as source/drain electrodes show typical ambipolar characteristics with very well balanced high hole and electron mobilities (μ_h = 0.024 cm² V^?1 s^?1 and μ_e = 0.056 cm² V^?1 s^?1). These simple and high-performing polymers are promising materials for ambipolar organic thin film transistors for low-cost CMOS-like logic circuits.     

Organic light-emitting diodes based on an ambipolar single crystal

Slice-like organic single crystals of 1,4-bis(2-cyano-2-phenylethenyl)benzene (BCPEB) are grown by the physical vapor transport (PVT) method, and exhibit a very high photoluminescence quantum efficiency (Φ_PL) of 75%. The ambipolar behavior of BCPEB single crystals are confirmed using the time of flight technique. The high efficiency and balanced (μ_h = 0.059 cm²/Vs and μ_e = 0.070 cm²/Vs) carriers’ mobility imply that the BCPEB single crystal is a promising light-emitting layer in the diodes structure. Intense green electroluminescence (EL) from a diode has been successfully demonstrated at an applied electric field of 2 × 10⁵ V/cm.     

A facile chemical reduction approach for effectively tuning thermoelectric properties of PEDOT films

Poly(3,4-ethylenedioxythiophene)–tosylate–polyethylene glycol–polypropylene glycol–polyethylene glycol (PEDOT–Tos–PPP) films were prepared via a vapor phase polymerization (VPP) method. The films possess good electrical conductivity (1550 S cm⁻¹), low Seebeck coefficient (14.9 μV K⁻¹) and thermal conductivity (0.501 W m⁻¹ K⁻¹), and ZT ∼ 0.02 at room temperature (RT, 295 K). Then, the films were treated with NaBH₄/DMSO solutions of different NaBH₄ concentrations to adjust the redox level. After the NaBH₄/DMSO treatment (dedoping), the electrical conductivity of the films continuously decreased from 1550 to 5.7 S cm⁻¹, whereas the Seebeck coefficient steeply increased from 14.9 to 143.5 μV K⁻¹. A maximum power factor of 98.1 μW m⁻¹ K⁻² has been achieved at an optimum redox level. In addition, the thermal conductivity of the PEDOT–Tos–PPP films decrease from 0.501 to 0.451 W m⁻¹ K⁻¹ after treated with 0.04% NaBH₄/DMSO solution. A maximum ZT value of 0.064 has been achieved at RT. The electrical conductivity and thermal conductivity (Seebeck coefficient) of the untreated and 0.04% NaBH₄/DMSO treated PEDOT–Tos–PPP films decrease (increases) with increasing temperature from 295 to 385 K. And the power factor of the films monotonically increases with temperature. The ZT at 385 K of the 0.04% NaBH₄/DMSO treated film is 0.155.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1 × 15 μm². The breakdown voltage was more than 7 V, the current could be more than 100 mA. The maximum output power can be more than 80 mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305 GHz at I_C = 50 mA and V_CB = 1.5 V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.     

Low optical power characterization of a base current-biased four-terminal dual-emitter heterojunction phototransistor

This paper reports on a four-terminal dual-emitter heterojunction phototransistor (4T-DEPT) with a base biased by a current source in comparison with a three-terminal dual-emitter heterojunction phototransistor (3T-DEPT). While only voltage can be used to tune the optical performance of the 3T-DEPT, voltage- and current-control modes are considered for the 4T-DEPT. One emitter (E2) serves as the voltage (V_E21)-controlled terminal at a fixed base biasing current while the other one (E1) is at the ground state. On the other hand, the base terminal controls the operation by applying an additional current (I_Bdc) bias when the V_E21 is constant. Therefore, voltage- and current-dependent characteristics will be detailed. Four operating regions exist in the voltage-dependent characteristics for both 3T- and 4T-DEPTs: negative-saturation, negative-tuning, positive-tuning, and positive-saturation regions. When the 4T-DEPT operates at the bias condition of V_E21 = 0.4 V, I_Bdc = 0.001 μA, and the incident optical power (P_in) of 0.423 μW, it shows the maximum current-dependent current-tuning efficiency and gain-tuning efficiency of 21.40 and 73.87 μA⁻¹, respectively. In addition to the power- and voltage-tunable optical gains, a current-tunable one is also available in the 4T-DEPT.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Enhancing pyroelectric and ferroelectric properties of PVDF composite thin films by dispersing a non-ferroelectric inclusion La2O3 for application in sensors

Thin films consisting of non-ferroelectric inclusions of La₂O₃ dispersed in a polymer matrix of polyvinylidene difluoride (PVDF) were prepared by the spin-coating method. It was found that the pyroelectric coefficient and remanent polarization of the composites were significantly improved to reach 42 μC/m² K and 84 mC/m², respectively. The enhancement of the measured coefficients in the composites can be achieved by introducing a very small amount (3 wt%) of La₂O₃. The figure of merit for material sensitivity, F_D has also improved from 69 to 86 μC/m² K¹. A local field in the inclusion site was shown to facilitate the poling procedure. A simple Maxwell–Wagner model in which the dc conductivity of the inclusion site was taken into consideration showed a good agreement with the obtained pyroelectric and ferroelectric properties.