Overdamped NbN junctions with NbNx barriers formed by plasma nitridation

We have fabricated NbN Josephson junctions with NbN_x barriers formed by plasma nitridation on the surface of the base superconductive NbN layer. Both nonhysteretic junctions (overdamped junctions) and small-hysteretic ones have been obtained at 4.2 K by changing plasma nitridation conditions. An overdamped junction showed a product of the critical current I_c and junction resistance R_n (an I_cR_n product) of 0.95 mV at 4.2 K and the I_c exponentially decreased with increasing temperature. On the other hand, a small-hysteretic junction showed Superconductor-Insulator-Superconductor (SIS)-like characteristics in the temperature dependence of I_c and its current–voltage characteristics changed to nonhysteretic ones at the temperature more than 8 K. The I_cR_n product for the junction was 0.91 mV at 8.2 K.     

Photophysical properties of nano Si/SiOx composites in Al/composite/mono Si structures for green light emitting and photodetector-Schottky diodes

The concept of the self-formation of a nanocrystallite (nc-) Si/SiO_x : Si_zO_yAl nanocomposite at the Al/oxidized porous silicon interface in the result of solid-phase processes between Al and oxidized porous Si (PS) and the influence of its composition on photophysical properties were developed and experimentally confirmed for the Si chip with optical intra-chip interconnect consisting of light emitting and photodetector diodes and alumina waveguide on oxidized PS surface with aluminum electrodes. The peculiarities of nanocomposite photophysical properties (the refractive index, photoluminiscence (PL) peak situation, PL spectrum shape in the green range) have been shown to be due to the quantum confinement effects (revealed by XPS, Raman spectroscopy) and depend on the Al presence in the nanocomposite (obtained by XPS, IR spectroscopy). The experimental confirmation of this concept is (i) the shift of the nc-Si valence band relatively to that of monocrystalline Si (c-Si) on 0.2–0.7 eV for nc-Si size in 2.5–6.5 nm range; (ii) the decrease of Si nanocrystallite size in the Al presence; (iii) the approach of the value of the refractive index of nc-Si : SiO : Si₂O₃ : Si_zO_yAl nanocomposite at λ=236 nm to that of porous Si with 45% porosity and (iv) the stable green PL spectra in the Si_zO_yAl presence in the nanocomposite.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing

2000 Å-SiO₂/Si(1 0 0) and 560 Å-Si₃N₄/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of ∼450°C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO₂∥Si₃N₄ wafer pair reached 2500 mJ/m², which was attained only above 1000°C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO₂ and Si₃N₄ films (Si/SiO₂∥Si₃N₄/Si) compared to the conventional method.     

Resistive switching properties of a thin SiO2 layer with CeOx buffer layer on n+ and p+ Si bottom electrodes

Resistive switching properties of a 2-nm-thick SiO₂ with a CeO_x buffer layer on p⁺ and n⁺ Si bottom electrodes were characterized. The distribution of set voltage (V_set) with the p⁺ Si bottom electrode devices reveals a Gaussian distribution centered in 4.5 V, which reflects a stochastic nature of the breakdown of the thin SiO₂. Capacitance–voltage (C–V) measurements indicate the trapping of electrons by positively shifting the C–V curve by 0.2 V during the first switching cycle. On the other hand, devices with the n⁺ Si bottom electrodes showed a broad distribution in V_set with a mean value higher than that of p⁺ Si bottom electrode devices by 0.9 V. Although no charge trapping was observed with n⁺ Si bottom electrode devices, a degradation in interface states was confirmed, causing a tail in the lower side of the V_set distribution. Based on the above measurements, the difference in the V_set can be understood by the work function difference and the contribution of electron trapping.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Sol–gel synthesized Titania nanoparticles deposited on porous polycrystalline silicon: Improved carbon dioxide sensor properties

Titania nanoparticles (TNPs) were synthesized by a sol–gel method in our laboratory using titanium tetrachloride as the precursor and isopropanol as the solvent. The particles׳ size distribution histogram was determined using ImageJ software and the size of TNPs was obtained in the range of 7.5–10.5 nm. The nanoparticle with the average size of 8.5 nm was calculated using Scherrer׳s formula. Homogeneous and spherical nanoparticles were characterized by X-ray diffraction (XRD), atomic force microscopy (AFM), field emission scanning electron microscopy (FESEM) and UV–visible spectroscopy (UV–vis). The X-ray powder diffraction analysis showed that the prepared sample (TNPs) has pure anatase phase. TNPs were deposited on porous polycrystalline silicon (PPS) substrate by electron beam evaporation. The TNPs thickness was 23±2 nm at 10⁻⁵ mbar pressure at room temperature. Porosity was performed by an anodization method. Since polycrystalline silicon wafers consist of different grains with different orientations, the pore size distribution in porous layer is non-uniform [1]. Therefore, the average diameter of pores can be reported in PPS layer analysis. Average diameter of pores was estimated in the range of 5 μm which was characterized by FESEM. The nanostructured thin films devices (Al/Si/PPS/TNPs/Al and Al/Si/PPS/Al) were fabricated in the sandwich form by aluminum (Al) electrodes which were also deposited by electron beam evaporation. Electrical measurements (I–V curves) demonstrated the semiconducting behavior of thin film devices. The gas sensitivity was studied on exposure to 10% CO₂ gas. As a result, conductivity of devices increased on exposure to CO₂ gas. The device with TNPs thin film (Al/Si/PPS/TNPs/Al) was more sensitive and, had better response and reversibility in comparison with the device without TNPs thin film (Al/Si/PPS/Al).     

Effects of bottom electrode and environmental insulator on thermal distribution of edge contact-type PRAM cell

Thermal characteristics of edge contact-type phase change random access memory cells have been investigated with different combinations of bottom electrode and insulator such as Ti and SiO₂, Ti and AlN, and TiN and AlN. At the same melting temperature on the programmable point of Ge₂Sb₂Te₅, we have determined heat flux for each combination: for the Ti and SiO₂, the heat flux is 3.5×10⁵ J/mm² s, for the Ti and AlN, and the TiN and AlN, they are 1.7×10⁶ and 1.9×10⁴ J/mm² s, respectively. These simulated results mean that the combination of TiN and AlN is the most effective for the fast response of phase changing from the amorphous to the crystalline and vice versa since the TiN has lower thermal conductivity than the Ti and the AlN has higher thermal conductivity than SiO₂.     

Optical and electrical characteristics of 17 keV X-rays exposed TiO2 films and Ag/TiO2/p-Si MOS device

This work presents the effect of varied doses of X-rays radiation on the Ag/TiO₂/p-Si MOS device. The device functionality was observed to depend strongly on the formation of an interfacial layer composed of SiO_x and TiO_y, which was confirmed by the spectroscopic ellipsometry. The XRD patterns showed that the as prepared TiO₂ films had an anatase phase and its exposure to varied doses of 17 keV X-rays resulted in the formation of minute rutile phase. In the X-rays exposed films, reduced Ti³⁺ state was not observed; however a fraction of Ti–O bonds disassociated and little oxygen vacancies were created. It was observed that the device performance was mainly influenced by the nature and composition of the interfacial layer formed at the TiO₂/Si interface. The spectroscopic ellipsometry was used to determine the refractive indices of the interfacial layer, which was 2.80 at λ=633 nm lying in between that of Si (3.87) and TiO₂ (2.11). The dc and frequency dependent electrical measurements showed that the interface defects (traps) were for both types of charge carriers. The presence of SiO_x was responsible for the creation of positive charge traps. The interface trap density and relaxation time (τ) were determined and analyzed by dc and frequency dependent (100 Hz–1 MHz) ac-electrical measurements. The appearance of peak in G/ω vs log (f) confirmed the presence of interface traps. The interface traps initially increased up to exposure of 10 kGy and then decreased at high dose due to compensation by the positive charge traps in SiO_x part of the interface layer. It was observed that large number of interface defects was active at low frequencies and reduced to a limiting value at high frequency. The values of relaxation time, τ ranged from 4.3±0.02×10⁻⁴ s at 0 V and 7.6±0.2×10⁻⁵ s at −1.0 V.     

Josephson array oscillator with microstrip resonators for submillimeter wave region

Shunted tunnel junctions with a small parasitic inductance have been developed for improving the operating frequency of Josephson array oscillators. The inductance was minimized by reducing the inductive length to 1 μm and was estimated to be about 40 fH. The analysis of resonant properties for the shunted junctions gave a high resonant frequency up to 1.4 THz. Josephson array oscillators were designed and fabricated to operate at near Nb gap frequency (700 GHz) using 11 shunted Nb/AlOx/Nb tunnel junctions with Nb microstrip resonators. Shapiro steps induced by Josephson oscillation were clearly observed above the Nb gap frequency (up to 830 GHz). By fitting the step height to the simulation result using the RLCSJ model, the output power of the Josephson oscillator to the load resistor was estimated to be about 0.1 μW at 680 GHz.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.     

Thermal conductivity of AlN thin films deposited by RF magnetron sputtering

Aluminum nitride (AlN) film, which is being investigated as a possible passivation layer in inkjet printheads, was deposited on a Si (1 0 0) substrate at 400 °C by radio frequency (RF) magnetron sputtering using an AlN ceramic target. Dependence on various reactive gas compositions (Ar, Ar:H₂, Ar:N₂) during sputtering was investigated to determine thermal conductivity. The crystallinity, grain size, and Al–N bonding changes by the gas compositions were examined and are discussed in relation to thermal conductivity. Using an Ar and 4% H₂, the deposited AlN films were crystalline with larger grains. Using a higher nitrogen concentration of 10%, a near amorphous phase, finer morphology, and an enhanced Al–N bonding ratio were achieved. A high thermal conductivity of 134 W/mk, which is nine times higher than that of the conventional Si₃N₄ passivation film, was obtained with a 10% N₂ reactive gas mixture. A high Al–N bonding ratio in AlN film is considered the most important factor for higher thermal conductivity.     

Charge injection in metal/organic/metal structures with ZnO:Al/organic interface modified by Zn1−xMgxO:Al layer

Aluminum-doped zinc oxide (ZnO:Al, AZO) electrodes were covered with very thin (∼6 nm) Zn_1−xMg_xO:Al (AMZO) layers grown by atomic layer deposition. They were tested as hole blocking/electron injecting contacts to organic semiconductors. Depending on the ALD growth conditions, the magnesium content at the film surface varied from x = 0 to x = 0.6. Magnesium was present only at the ZnO:Al surface and subsurface regions and did not diffuse into deeper parts of the layer. The work function of the AZO/AMZO (x = 0.3) film was 3.4 eV (based on the ultraviolet photoelectron spectroscopy). To investigate carrier injection properties of such contacts, single layer organic structures with either pentacene or 2,4-bis[4-(N,N-diisobutylamino)-2,6-dihydroxyphenyl] squaraine layers were prepared. Deposition of the AMZO layers with x = 0.3 resulted in a decrease of the reverse currents by 1–2 orders of magnitude and an improvement of the diode rectification. The AMZO layer improved hole blocking/electron injecting properties of the AZO electrodes. The analysis of the current-voltage characteristics by a differential approach revealed a richer injection and recombination mechanisms in the structures containing the additional AMZO layer. Among those mechanisms, monomolecular, bimolecular and superhigh injection were identified.     

Direct imprint of Al foil for metallization of high-aspect ratio Al lines in nano/micro patterned SiO2/Si

Patterning techniques of Al micro/nano-structures become more and more critical as optical components and microelectronic devices continue to be scaled down. In this work, we fabricated gap-filled Al lines in SiO₂/Si masters by using the direct thermal imprint of molten Al. As a result, gap-filled Al lines with width ranging from 0.25 to 20 μm and depth ranging from 6 to 127 μm could be achieved without any further processing step such as CVD and PVD. The process studied here has shown the possibility to extend trench filling capability to 0.25 μm structures with 24:1 aspect ratio, which are difficult to be obtained by other conventional Al metallization methods.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Laser-induced forward transfer of polythiophene-based derivatives for fully polymeric thin film transistors

Polymeric thin-film transistors (pTFTs) have been fabricated by pulsed-laser printing of semiconductor and conductor polythiophene-based derivatives. Thin solid layers of semiconducting poly(3,3′″ didodecylquaterthiophene) (PQT-12) have been transferred by a laser-induced forward transfer (LIFT) technique on Si/SiO₂ receiver substrates. Optimization of the transfer conditions and of the pixels morphologies has been realized. A marked improvement in the quality of the pixels has been observed, in terms of morphology and structure, by reducing the environmental pressure to 90 mbar during LIFT. Subsequently, poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonate) (PEDOT:PSS) has also been laser-printed and used as source/drain electrodes in the transistor configuration. Functional polymeric transistors have been obtained with high field-effect mobility up to 2 × 10⁻² cm² V⁻¹ s⁻¹ together with current modulation of 10⁴.     

Effect of the film thickness on the crystal structure and ferroelectric properties of (Hf0.5Zr0.5)O2 thin films deposited on various substrates

In this work, the effect of the film thickness on the crystal structure and ferroelectric properties of (Hf_0.5Zr_0.5)O₂ thin films was investigated. The thin films were deposited on (111) Pt-coated SiO₂, Si, and CaF₂ substrates with thermal expansion coefficients of 0.47, 4.5, and 22×10⁻⁶/°C, respectively. From the X-ray diffraction measurements, it was found that the (Hf_0.5Zr_0.5)O₂ thin films deposited on the SiO₂ and CaF₂ substrates experienced in-plane tensile and compressive strains, respectively, in comparison with the films deposited on the Si substrates. For films deposited on all three substrates, the volume fraction of the monoclinic phase increased with increasing film thickness, with the SiO₂ substrate having the lowest monoclinic phase volume fraction at all film thicknesses tested. The grain size of the films, which is an important factor for the formation of the ferroelectric phase, remained almost constant at about 10 nm in diameter regardless of the film thickness and type of substrate utilized. Ferroelectricity was observed for the 17 nm-thick films deposited on SiO₂ and Si substrates, and the maximum remanent polarization (P_r) value of 9.3 µC/cm² was obtained for films deposited on the SiO₂ substrate. In contrast, ferroelectricity with P_r=4.4 µC/cm² was observed only for film on SiO₂ substrate in case of 55 nm-thick films. These results suggest that the films under in-plane tensile strain results in the larger ferroelectricity for 17 nm-thick films and have a ferroelectricity up to 55 nm-thick films.     

Characterization of interfacial reaction and chemical bonding features of LaOx/HfO2 stack structure formed on thermally-grown SiO2/Si(1 0 0)

A stack structure consisting of ～1.5 nm-thick LaO_x and ～4.0 nm-thick HfO₂ was formed on thermally grown SiO₂ on Si(1 0 0) by MOCVD using dipivaloymethanato precursors, and the influence of N₂ annealing on interfacial reaction for this stack structure was examined by using X-ray photoelectron spectroscopy and Fourier transform infrared attenuated total reflection. We found that compositional mixing between LaO_x and HfO₂ becomes significant from 600 °C upwards and that interfacial reaction between HfLa_yO_z and SiO₂ proceeds consistently at 1000 °C in N₂ ambience.