Thermal analysis of active layer in organic thin-film transistors

This paper reports on the direct thermal observation of the pentacene – based organic thin-film transistors (OTFTs) under the real operating conditions. Liquid crystal (LC) spreading method was utilized for the thermal investigation of an active layer of the OTFT package. Temperature variation in the OTFT package was recorded for the different input power and significant heat generation was observed in the confined active layer. Detailed thermal performance of the OTFT package was projected using a Computational Fluid Dynamics (CFD) method as well. It was shown that the driving of the OTFT package with the drain voltage of ?15 V resulted in the active layer temperature of about 53.2 °C. The result indicates that the device design with effective thermal dissipation is imperative for reliable operation of the OTFT package.     

Thermal analysis of preswitching characteristics of a thin-film amorphous-chalcogenide switch

The preswitching nonohmic behaviour of amorphous-semiconductor switches could result from either Joule heating or space-charge-limited currents. After the `forming? of a virgin device, electron-microscope examinations have revealed a channel whose composition differs significantly from the matrix. Also, the I/V characteristics of the blocking states of virgin and formed devices are significantly different. The preswitching I/V characteristics of a Ge15Te81S4 chalcogenide-glass switch at 300 K have been explained by Joule heating in the formed channel, with an estimated temperature rise of 25 degC above ambient at the centre of a monostable switch.     

红外焦平面探测器封装结构热应力分析

红外焦平面探测器是一个主要由引线基板、硅读出电路、铟柱和探测器芯片组成的多层结构。由于材料层间热膨胀系数的差异,低温时探测器中会产生相当大的热应力,对探测器温度循环可靠性影响严重。为了考察红外焦平面探测器低温下的热应力情况,建立了探测器结构的有限元分析模型;利用该模型分析了引线基板热膨胀系数、弹性模量,及其厚度分别对Si、CdZnTe衬底类型的探测器热失配应力和形变的影响;根据对这两种类型探测器的分析结果,分别提出了相应的改进方法,并对方法进行了计算验证。     

Thermal transport properties of gold-covered thin-film silicon dioxide

Due to continued miniaturization, the performance and reliability of electronic devices composed of multiple thin layers of material are highly dependent on effective thermal management. Since the thermal properties of thin films, such as SiO/sub 2/, can vary considerably from bulk values, the determination of those properties (as well as the interface resistance between SiO/sub 2/ and adjacent layers) is critical for the purposes of design. In this work, a transient thermo-reflectance system has been employed to measure the thermal characteristics of thin-film SiO/sub 2/ layers. Results show that for layers of SiO/sub 2/ in the range of 100-1000 /spl Aring/, the intrinsic thermal conductivity (TC) is independent of thickness and smaller than the traditionally reported value of bulk silicon dioxide (1.4 W/m-K). The intrinsic value was measured to be around 90% (1.27 W/m-k) and 75% (1.05 W/m-k) of the latter bulk value for thermally grown (TG) and ion beam sputtered (IBS) oxides, respectively. The thermal interface resistances of TG and IBS SiO/sub 2/ films were measured at 1.68 /spl times/ 10/sup -8/ m/sup 2/-K/W and 2.58 /spl times/ 10/sup -8/ m/sup 2/-K/W, respectively. If a chromium film of around 100 /spl Aring/ is deposited between the gold and SiO/sub 2/ layers, the interface thermal resistance improves to 0.78 /spl times/ 10/sup -8/ m/sup 2/-K/W for TG films and 1.15 /spl times/ 10/sup -8/ m/sup 2/-K/W for IBS films. Thus, the effective thermal resistance of SiO/sub 2/ thin-films (i.e., with interface effects) is up to one order of magnitude smaller than the values reported for bulk SiO/sub 2/.     

薄膜应力激光测量方法分析

总结了薄膜应力的一些测量方法.分析了利用测量基片弯曲曲率的激光宏观变形分析法———激光干涉法、激光束偏转法的理论依据及其测量原理,计算了各种测量方法的测量精度.激光干涉法的精度可达0.92%,可测量的最小应力值为15.7MPa;激光束偏转法较低,为2.12%,可测量的最小应力值为25.5MPa,空间分辨率低,约为100μm.     

MEMS多层结构的热应力分析

温度载荷能够引起MEMS多层薄膜结构发生翘曲和分层等失效模式,而界面应力则是引起这些失效的直接原因。根据Suhir.E的双金属带热应力分布理论,对温度载荷作用下MEMS界面中的剪应力和剥离应力的分析表明,这两种应力随着与界面中心距离的增大呈指数增加,在界面端处达到最大值。界面应力与材料热膨胀系数和所加载温度呈线性相关,另外还与两材料层的厚度密切相关。以铜/铬组成的双层结构为例,利用Matlab数值仿真研究了界面应力与材料层厚度的关系,结果表明,界面应力与两材料层厚度比有关,当铜层和铬层厚度比为1.5时,层间剪应力和剥离应力均较小,可有效提高MEMS结构的可靠性,降低分层失效的概率。     

LOCOS-induced stress effects on thin-film SOI devices

LOCOS-induced stress effects on thin-film SOI devices are investigated. We show that as the field oxide thickness increases, degradation (enhancement) of nMOSFET's (pMOSFET's) I-V characteristics becomes increasingly pronounced. The total degradation or enhancement of I-V characteristics can reach ~40% of drive current for devices under certain processing conditions. Estimated stress results using four-point bending measurement show that the stress level on the silicon film is of order 1200 MPa for devices with ~40% of I-V degradation/enhancement. We attribute the stress phenomenon to the volumetric expansion of field oxide during the LOCOS process     

同一PCB板上不同封装结构的热应力分析

基于ABAQUS有限元分析软件,对同一PCB板上QFP和PBGA两种不同封装结构,在温度循环载荷下的应力场进行了研究,并对不同封装结构的性能进行了比较分析。结果表明:在温度循环载荷下,无论何种封装组件,越靠近PCB板的边缘,器件的应力值越大;在同等条件下,PBGA封装器件的应力值高于QFP封装器件;以同类封装器件中最大应力值的10%为临界点,封装器件中应力值比最大应力值小10%以上的为非薄弱元器件,其余均定义为薄弱元器件。根据该定义,对前述5组QFP和PBGA封装器件,除位于PCB板中间位置的外,其余各组封装器件均为薄弱元器件。     

聚合物整体灌装电路板热应力分析

电路板的聚合物整体灌装是一种提高电子器件在极端工况下可靠性的方法。针对该方法所面临的热应力失效问题,采用有限元数值方法研究了含15个元器件的整体灌装电路板在环境温度改变和器件产热两种热载荷下的热应力分布,并通过参数化模拟分析了不同几何和材料参数对元器件及其接合层中热应力分布的影响。结果表明整体灌装加剧了IC器件及其接合层的热应力,该模拟工作为提高整体灌装方案的热应力可靠性提供参考。     

Interfacial shear stress, peeling stress, and die cracking stressin trilayer electronic assemblies

Interfacial shear stress, peeling stress, and die cracking stress due to thermal and elastic mismatch in layered electronic assemblies are one of the major causes of the mechanical failure of electronic packages. A simple but rather accurate method is developed to estimate these thermal stresses for packages with different layer lengths. For layered electronics with thin adhesives, analytical expressions are obtained for interfacial shear stress and peeling stress, and they agree well with the finite element analysis, especially when the moduli of adhesive layers are significantly lower than the moduli of the other layers. An analytic expression of die cracking stress is also obtained for multilayer electronic assemblies     

Control of the performance of polysilicon thin-film transistor byhigh-gate-voltage stress

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFTs) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high gate voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO₂ interface     

关于光缆接头盒中光纤涂层脱落问题的分析

本文通过对一起接头盒中光纤涂覆层脱落的案例进行分析，提出了避免问题出现的方法和光缆接续时的注意事项。     

Thermal stress analysis of composite encapsulants with a spherical adhesive interface

Semiconductor devices packaged in a rigid epoxy often utilize an internal compliant coating to minimize stresses transferred to the chip. Thermal stress analysis of such a composite encapsulating system with a spherical adhesive interface has been performed. The compliant layer encounters the highest tensile stress level upon cooling from the epoxy molding temperature due to the mismatch of thermal expansion coefficients and elastic properties within the composite. Indeed, this stress may readily exceed the tensile strength of the inner coating resulting in its fracture. In order to facilitate a systematic search for compatible plastics which assure package integrity, a useful figure of merit which is suggested by the analysis, the composite modulus, has been devised.     

Analysis of bias stress on unpassivated hydrogenated amorphoussilicon thin-film transistors

Both the subthreshold slope and the threshold voltage in inverted-staggered amorphous silicon thin-film transistors (a-Si:H TFTs) are vulnerable to metastable changes in the density of states (DOS) due to Fermi level displacement. In previous work, we have used passivated and unpassivated TFTs to distinguish between the effects of bulk states and interface states at the top passivating nitride interface. Here we report the results of experimental measurements and two-dimensional (2-D) simulations on unpassivated TFTs. Since there are no top interface states, all the observed changes are due solely to the bulk DOS. The subthreshold current activation energies in a-Si:H TFTs are compared for n-channel nonpassivated TFTs before and after bias stress. The experimental results agree well with the 2-D simulations, confirming that the dependence of subthreshold current activation energy on gate bias reveals the distribution of the DOS in energy but cannot resolve the magnitude of features in the DOS. This type of analysis is not accurate for TFTs with a top passivating nitride, since the activation energies in such devices are affected by the interfere states     

A ray-optical analysis of thin-film polarization converters

A compact formula is given for the Goos-Haenchen shifts occurring for total internal reflection of light from anisotropic media. This is used in a coupled-wave analysis of polarization conversion in thin-film waveguides deposited on optically birefringent substrates. A numerical example illustrates the considerable influence of the Goos-Haenchen shifts on the conversion length.     

Nanoscale thermally induced stress analysis by complementary Scanning Thermal Microscopy techniques

Thermally induced stress is determined using boundary values obtained by complementary Scanning Joule Expansion Microscopy and Scanning Thermal Microscopy. The stress function is then solved with the Finite Element Method. Surface stress analysis as well as stress analysis of multilayered structures are performed in order to demonstrate the application of the developed measurement technique to reliability investigations.     

基于哈特曼原理的薄膜应力在线测量系统

介绍了一种基于哈特曼传感器的薄膜应力在线检测系统.哈特曼透镜阵列将待测量表面划分成若干小区域,通过测量每个小区域成像光斑的相对位置变化来获得整个测量表面的变形量,将测得的变形量代入到薄膜应力与基板表面变形的关系式中,求得薄膜应力.通过对影响光斑质心探测精度的各种因素进行分析,提出使用加阈值的一阶矩法,精确计算光斑质心,结合高灵敏度的CMOS探测器,使系统的面形测量精度达到15.7 nm,应力测量灵敏度优于3.3 MPa,实现了薄膜应力测量的高灵敏度与在线测量的统一.最后通过对TiO2,SiO2单层膜的在线测量,验证了系统的灵敏度与稳定性,能够完全满足薄膜应力分析的需要.     

叠层芯片封装元件热应力分析及焊点寿命预测

研究了温度循环载荷下叠层芯片封装元件(SCSP)的热应力分布情况,建立了SCSP的有限元模型。采用修正后的Coffin-Masson公式,计算了SCSP焊点的热疲劳寿命。结果表明:多层芯片间存在热应力差异。其中顶部与底部芯片的热应力高于中间的隔离芯片。并且由于环氧模塑封材料、芯片之间的热膨胀系数失配,芯片热应力集中区域有发生脱层开裂的可能性。SCSP的焊点热疲劳寿命模拟值为1 052个循环周,低于单芯片封装元件的焊点热疲劳寿命(2 656个循环周)。     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed     

An analysis of deep depletion thin-film MOS transistors

Consideration is given to the problems associated with the use of an insulated gate to obtain depletion in the channel of a field-effect transistor. It is shown that if an inversion layer forms at the insulator semiconductor interface before the channel is completely depleted complete pinch-off of drain current by the gate will not be observed. It is further shown that channel pinch-off at the drain will always occur and, hence, that drain current saturation will always be observed. A quantitative analysis based on the proposed model is performed and theoretical expressions for the device behavior are derived and plotted. The analysis of the device is divided into two ranges, a high-frequency range and a low-frequency range, where the dividing frequency is the frequency response of the surface inversion layer. This dividing frequency is generally orders of magnitude lower than the upper operating frequency limit of the transistor itself. Finally, the theoretical results are compared with experiment and shown to be in good agreement.