Life test of an X-band MMIC multi-function chip for active phased array radar applications

A 1000-h steady state life test at a temperature of 125 °C was performed on ten X-band MMIC multifunction chips for use in active phase array radar systems. Internal switches, phase shifters, and attenuators were operated through an integrated serial-to-parallel converter under the five-second stepped external control signal for the life test period. None of the ten samples failed under the failure criteria based on the JEP118 standard. The calculated failure rate using the Chi Square Statistic was 1.6 e⁻⁶ failures/h for the 90% confidence level. Maximum DC current variation was +16% for an initial value. Maximum variations of small signal gain, phase shift, and attenuation were 0.96 dB, 2°, and 0.17 dB, respectively, over a frequency range of 8.5–10.5 GHz.     

Monitoring of thermo-mechanical stress via CMOS sensor array: Effects of warpage and tilt in flip chip thermo-compression bonding

Flip chip thermo-compression bonding (TCB) involves the use of heat and pressure to simultaneously form interconnections for microelectronic packaging. In-situ measurements of thermo-mechanical stresses that arise during this bonding process could provide unique insight to help better understand the TCB process. A 4 mm × 3 mm × 500 μm complementary metal-oxide-semiconductor (CMOS) sensor chip with an 8 × 8 array of Au-bumped sensor pads was developed for this purpose. It was designed to record XYZ force and temperature signals from bump locations, during a simulated flip chip process similar to TCB.In-situ measurements during simulated TCB events proved useful for tilt detection, thermal gradient characterization, and thermal expansion measurements. Further interpretation of the signals proved tilt and other thermo-mechanical effects were induced by thermal expansion mismatches. The most thermo-mechanically stressful stage of bonding was found to occur during thermal transients, specifically during bond head ramping. Further analysis concluded the actual time necessary to heat the bumps was less than 0.5 s. Finally, the lateral thermal gradient across the sensor chip was calculated to be smallest in the central bump locations, and largest in the bump array corners due to warpage, tilt, and heat sink effects of the digital logic region.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm². This work has been successfully applied in 13-bit 200MSPS A/D converter.     

Modular sensor chip design for package stress evaluation and reliability characterisation

A modular test chip comprising an array of 2 mm square modules has been designed and fabricated. The maximum chip size can be up to 10 mm square, i.e. a 5 × 5 array of modules. The motivation behind the test chip is primarily the need to address reliability concerns in the use of copper wire bonding. It is known that the move to replace gold wire bonding with copper, driven primarily by the escalating price of gold, leads to reliability challenges at the interfaces between the wire bonds, the bond pads and the mould compound. Its function is to address. The chip comprises daisy chain structures to monitor changes of wire bond resistance and leakage current, large and small area stress sensors to measure stress on the chip associated with die attach and moulding, and comb and triple track sensors to study corrosion and moisture penetration related to mould compound.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

Modeling and design of a monolithically integrated power converter on SiC

To fully explore the high temperature and high power density potential of the 4H-SiC material, not only power devices need to be fabricated on SiC, but also the circuitries for signal generation/processing, gate driver and control. In this paper, static and dynamic characteristics of SiC lateral JFET (LJFET) devices are numerically simulated and compact circuit models developed. Based on these models, analog and digital integrated circuits functional blocks such as OPAMP, gate driver and logic gates are then designed and simulated. Finally, a fully integrated power converter including pulse-width-modulation circuit, over-temperature protection circuit and a power boost converter is designed and simulated. The converter has an input of 200 V and an output voltage of 400 V, 2.5 A, operating at 1 kW and 5 MHz.     

Single flux quantum one-decimal-digit RNS adder

Residue number system (RNS) arithmetic has a promising role for fault-tolerant high throughput superconducting single flux quantum (SFQ) circuits for digital signal processing (DSP) applications. We have designed one of the basic computational blocks used in DSP circuits, one-decimal-digit RNS adder. A new design for its main component, the single-modulus adder, has been developed. It combines simple and robust RSFQ elementary cells, both combinational and sequential. The central units are a circular shift register, a code converter, and the clock control circuitry. Our mod5 adder employs 195 Josephson junctions, consumes 50 μW of power, and occupies an area of less than 2 mm². Chips were fabricated at HYPRES, Inc. using 1 kA/cm² low-T_c Niobium technology. The mod5 adder was successfully tested at low speed, and gave experimental bias margins of ±26%.     

Auxiliary components for kilopixel transition edge sensor arrays

We have fabricated transition edge sensor bolometer focal plane arrays sensitive to mm-submillimeter (0.1–3 THz) radiation for the Atacama Cosmology Telescope (ACT), which will probe the cosmic microwave background at 145, 215, and 280 GHz. Central to the performance of these bolometers is a set of auxiliary resistive components. Here we discuss shunt resistors, which allow for tight optimization of bolometer time constant and sensitivity. Our shunt resistors consist of AuPd strips grown atop interdigitated superconducting MoN_x wires. We can tailor the shunt resistance by altering the dimensions of the AuPd strips and the pitch and width of the MoN_x wires and can fabricate all of the shunts necessary for a kilopixel focal plane bolometer array on a single 4″ wafer. By modeling the resistance dependence of these parameters, a variety of different 0.75 ± 0.05 mOhm shunt resistors have been fabricated. This variety includes different shunts which have MoN_x wires with wire width equal to 1.5 and 10 μm and pitch equal to 4.5 and 26 μm, respectively. Our ability to set the resistance of the shunts hints at the scalability of our design. We have also integrated a SiO₂ capping layer into our shunt resistor fabrication scheme, which inhibits metal corrosion and eventual degradation of the shunt. Consequently, their robustness coupled with their high packing density makes these resistive components attractive for future kilopixel detector arrays.     

A low power and small area digital self-calibration technique for pipeline ADC

A digital self-calibration implementation with discontinuity-error and gain-error corrections for a pipeline analog-to-digital converter (ADC) is presented. In the proposed calibration method, the error owing to each reference unit capacitor of the multiplying D/A converter is measured separately using a calibration capacitor and an enhanced resolution back-end pipeline ADC acting as an error quantizer. The offset and finite open loop DC-gain of the operational amplifier and capacitor mismatches, the reference voltage mismatch can all be calibrated. The calibration can be achieved by that only used addition and subtraction. Hence, it needs low power and area consuming. A prototype ADC with the proposed calibration was fabricated on a 0.5 μm double-poly triple-metal CMOS process. The power consumption and area of the calibration circuit are only 10.1 mW and 1.05 mm², respectively. At a sampling rate of 30 MS/s, the calibration improves the DNL and INL from 2.59 LSB and 14.98 LSB to 0.72 LSB and 1.82 LSB, respectively. For a 1.25 MHz sinusoidal signal, the calibration improves the signal-to-noise-distortion ratio and spurious-free dynamic range from 43.1 dB and 52.1 dB to 75.51 dB and 83.61 dB, respectively. The 12.25 effective number of bits at 30 MS/s ADC consumes a total power of 136 mW.     

An 8 bit, 100 kS/s,switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm². The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×10²⁰, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.     

Oscillation-controlled CMOS ring oscillator for wireless sensor systems

This paper presents a ring oscillator with the function of the oscillation controlled for wireless sensor systems (WSSs). The proposed oscillator consists of a NAND gate, 4 inverters, and 1-, 3-, 9-times buffer stage. Operation of it is controlled by the NAND gate. The oscillator can reduce the power loss because the oscillator is oscillated during only high level input. The proposed oscillator was designed and fabricated by 2.5 μm CMOS technology, through which it is possible to realize a WSS on a single chip because a sensor and an oscillator can be fabricated concurrently.The frequency tuning range of the oscillator was found to be approximately 90–152 MHz and the output power of the oscillator was ?8.42 dBm. The measured phase noise is ?99.35 and ?102.59 dBc/Hz at 1 and 5 MHz offsets, respectively, from the carrier of 152 MHz. Power consumption of the oscillator is determined by the duty cycle of the input signal pulse, and the range of power consumption was measured as 1.5–45 mW at the duty cycle of 1.0.     

Heuristic receiver for implantable UWB applications

High data rate implantable wireless systems come with many challenges, chief among them being low power operation and high linearity. A low noise amplifier (LNA) designed for this application must include high gain, low noise figure (NF) and better linearity at low power consumption within the required frequency band. The down converter also requires a passive mixer to achieve low power and better linearity. In this paper, design is based on an Impulse Response (IR) Ultra-wideband (UWB) receiver operating at (3.1–5) GHz implemented in 0.25 μm CMOS Silicon on Sapphire (SOS). This paper reports the design and measurement of a UWB receiver with a designed and measured linearity of 17 dBm, a gain of 30.5 dB and a minimum NF of 4.5 dB, which make it suitable for implantable radio applications.     

A low-distortion multi-bit sigma–delta ADC with mismatch-shaping DACs for WLAN applications

A low-distortion feed-forward MASH2_4b-2_4b sigma–delta analog-to-digital converter (ADC) for wireless local area network (WLAN) applications was presented. The converter exhibits improved performances than the ADCs which have been presented to date by adding a feedback factor in the second stage and employing a 2nd-order noise-shaping dynamic element matching (DEM) scheme. The feedback factor induces a zero in the noise transfer function (NTF) and therefore improves the in-band signal to noise and distortion ratio (SNDR) of the modulator. The mismatch-shaping DEM was introduced and applied to the 4-bit DACs in this paper to improve the resolution and linearity of the ADC. Fabricated in a 0.18 μm CMOS process with single 1.8 V supply voltage, the converter achieves a peak SNDR of 85.4 dB over a 10 MHz bandwidth which implies an effective number of bits (ENOB) of 13.90-bit. The spurious free dynamic range (SFDR) is –94 dB for a 1.25 MHz@–6dBFS input signal at 160 MHz sampling frequency. The occupied area is 0.44 mm² and dissipation power 23.4 mW.     

Accurate operation of a CMOS integrated temperature sensor

A high-accuracy temperature sensor is designed by applying the temperature characteristics of substrate bipolar transistor in CMOS technology. Initial accuracy of the temperature sensor can be improved by chopper amplifiers and dynamic element matching. Using these two methods, the circuit realization of reference voltage is also described. Simulation results show that the inaccuracy is within×0.4 °C from ?40 to +100 °C. Experimental results, obtained from circuits fabricated in 0.5 μm CMOS process, indicate that the sensor is inaccurate within×0.7 °C from ?40 to +100 °C. The power dissipation is 0.35 mW and the chip area is 889 μm×620 μm. Compared with previously reported work, the temperature sensor in the paper has lower inaccuracy without calibration.     

Design issues in ultra-fast ultra-low-power superconductor Batcher-banyan switching fabric based on RSFQ logic/memory family

The results are presented of the feasibility study of ultra-fast low-power superconductor digital switches based on Rapid Single-Flux-Quantum (RSFQ) technology. RSFQ-based crossbar, Batcher-banyan, and shared bus switching fabrics are considered, and the complexity and performance parameters of these circuits have been estimated. The results show that the proposed SFQ digital switches with overall throughput of 5.76 Tbps operating at an internal clock frequency of ∼60 GHz and dissipating as low as 45 mW power per fabric could effectively compete with their semiconductor and photonic counterparts. The most compact and low-power architecture, the Batcher-banyan switching fabric with TDM switching elements, has been selected for implementation and will be discussed in the paper in detail.     

All-digital thermal distribution measurement on field programmable gate array using ring oscillators

In this paper, a digital method for transient temperature distribution measurement of field programmable gate array (FPGA)-based systems is proposed. The smart thermal sensors used rely on correspondence between the delay and temperature in a ring oscillator. The tested temperature was converted into a time signal with a thermally-sensitive width. The output frequency is read out by a counter with a scan path, and then, transited to PC by a Universal Serial Bus (USB) interface. We capture the infrared images of the FPGA chip by infrared camera. The images were compared with the thermal map of the die constructed using an array of sensors. The tested temperature error varies by less than 1.6 °C in the range from 20 °C to 90 °C, and the maximum sampling rate is 330 Hz.     

A single-bit sampling demodulator for biomedical implants

A phase-shift keying (PSK) demodulator is demonstrated for the target application of low power and high data rate inductive links. The demodulator based on the single-bit sampling demodulation scheme is capable of operating in binary, quadrature, 8-, and 16-PSK mode. The prototype chip realized in 0.18-µm CMOS process can demodulate up to 1.25 MSymbol/s at 5-MHz carrier frequency. It occupies 240×310 µm² and consumes 140 µA from 1.2 V.     

Proton-induced SEU in SiGe digital logic at cryogenic temperatures

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.     

A low power MEMS gas sensor based on nanocrystalline ZnO thin films for sensing methane

Nanocrystalline ZnO based sensor using micromachined silicon substrate has been reported for efficient detection of methane as opposed to conventional SnO₂ based micromachined sensors for its higher compatibility to silicon IC technology and greater response. A suitably designed nickel microheater has been fabricated on to the micromachined Si platform. The optimum temperature for highest response magnitude and lowest response time were found to be 250 °C although relatively high (76.6%) response is obtained even at as low as 150 °C. Our study showed quite high response magnitude (87.3%), appreciably fast response time (8.3 s) and recovery time (17.8 s) to 1.0% methane at 250 °C. The sensor showed appreciably fast response (14.3 s) and recovery time (28.7 s) at 150 °C. The power consumption at an operating temperature of 250 °C was 120 mW and at 150 °C is only ～70 mW. Moreover, this type of sensor was found to give fairly appreciable response for lower methane concentrations (0.01%) also. For higher methane concentrations (>0.5%) response is detectable even at 100 °C where the power consumption is only ～40 mW.