Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Microbridge preparation through spincoating and photolithography without etching

It is possible to produce HTSC thin films of polymer metal precursors by the simple spincoating technique. This method can be used to manufacture of Y–Ba–Cu–O- and Bi–Sr–Ca–Cu–O–HTSC thin films. The microbridges are generated into the precursor film by photolithography. The etching process step is cancelled. After that the superconducting phases are formed at 950°C respectively 865°C during the tempering process. The HTSC structures serve as a previous stage for SNS contact. The critical temperatures (T_c) measured on the 20 and 200 μm wide microbridges are 82 K for Y–Ba–Cu–O and 108 K for Bi–Sr–Ca–Cu–O. The critical current density (j_c) obtained is 10⁵ A/cm² for 65 K.     

High power 4H–SiC pin diodes (10 kV class) with record high carrier lifetime

The hole lifetime τ_p in the n-base and isothermal (pulse) current–voltage characteristics have been measured in 4H–SiC diodes with a 10 kV blocking voltage (100 μm base width). The τ_p value found from open circuit voltage decay (OCVD) measurements is 3.7 μs at room temperature. To the best of the authors’ knowledge, the above value of τ_p is the highest reported for 4H–SiC. The forward voltage drops V_F are 3.44 V at current density j = 100 A/cm² and 5.45 V at j = 1000 A/cm². A very deep modulation of the blocking base by injected non-equilibrium carriers has been demonstrated. Calculations in term of a simple semi-analytical model describe well the experimental results obtained.     

Fabrication of single crystal field-effect transistors with phenacene-type molecules and their excellent transistor characteristics

Single crystal field-effect transistors (FETs) using [6]phenacene and [7]phenacene show p-channel FET characteristics. Field-effect mobilities, μs, as high as 5.6 × 10^?1 cm² V^?1 s^?1 in a [6]phenacene single crystal FET with an SiO₂ gate dielectric and 2.3 cm² V^?1 s^?1 in a [7]phenacene single crystal FET were recorded. In these FETs, 7,7,8,8-tetracyanoquinodimethane (TCNQ) was inserted between the Au source/drain electrodes and the single crystal to reduce hole-injection barrier heights. The μ reached 3.2 cm² V^?1 s^?1 in the [7]phenacene single crystal FET with a Ta₂O₅ gate dielectric, and a low absolute threshold voltage |V_TH| (6.3 V) was observed. Insertion of 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F₄TCNQ) in the interface produced very a high μ value (4.7–6.7 cm² V^?1 s^?1) in the [7]phenacene single crystal FET, indicating that F₄TCNQ was better for interface modification than TCNQ. A single crystal electric double-layer FET provided μ as high as 3.8 × 10^?1 cm² V^?1 s^?1 and |V_TH| as low as 2.3 V. These results indicate that [6]phenacene and [7]phenacene are promising materials for future practical FET devices, and in addition we suggest that such devices might also provide a research tool to investigate a material’s potential as a superconductor and a possible new way to produce the superconducting state.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Organic light-emitting diodes based on an ambipolar single crystal

Slice-like organic single crystals of 1,4-bis(2-cyano-2-phenylethenyl)benzene (BCPEB) are grown by the physical vapor transport (PVT) method, and exhibit a very high photoluminescence quantum efficiency (Φ_PL) of 75%. The ambipolar behavior of BCPEB single crystals are confirmed using the time of flight technique. The high efficiency and balanced (μ_h = 0.059 cm²/Vs and μ_e = 0.070 cm²/Vs) carriers’ mobility imply that the BCPEB single crystal is a promising light-emitting layer in the diodes structure. Intense green electroluminescence (EL) from a diode has been successfully demonstrated at an applied electric field of 2 × 10⁵ V/cm.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Nonohmic properties of V/Mn/Nb/Gd co-doped zinc oxide semiconducting varistors with low-temperature sintering process

The microstructure and nonohmic properties of the ZnO–V₂O₅–MnO₂–Nb₂O₅–Gd₂O₃ (ZVMNG) semiconducting varistors were systematically investigated at low sintering temperature. With increasing sintering temperature, the average grain size increased from 4.1 to 11.7 μm, the sintered densities decreased from 5.54 to 5.42 g/cm³, and the breakdown field decreased noticeably from 7138 to 920 V/cm. The sample sintered at 900 °C exhibited excellent nonohmic properties, which are 66.1 in the nonohmic coefficient and 77 μA/cm² in the leakage current density.     

Influence of plasma treatment of ITO surface on the growth and properties of hole transport layer and the device performance of OLEDs

Surface energy of indium tin oxide (ITO) surfaces treated by different plasmas, including argon (Ar–P), hydrogen (H₂–P), carbon tetrafluoride (CF₄–P), and oxygen (O₂–P), was measured and analyzed. The initial growth mode of hole transport layers (HTLs) was investigated by atomic force microscope observation of thermally deposited 2 nm thick N,N′-bis(1-naphthyl)-N,N′-diphenyl-1,1′-biphenyl-4,4′-diamine (NPB) on the plasma treated ITO surfaces. The results show that different plasma treatments of ITO influence the growth of HTLs in significantly different ways through the modification of surface energy, especially the polar component. The O₂–P and CF₄–P were found to be most effective in enhancing surface polarity through decontamination and increased dipoles, leading to more uniform and denser nucleation of NPB on the treated ITO surfaces. It was further found that increased density of nucleation sites resulted in a decreased driving voltage of OLEDs. Under the same fabricating conditions, a lowest driving voltage of 4.1 V was measured at a luminance of 200 cd/m² for the samples treated in CF₄–P, followed by the samples treated in O₂–P (5.6 V), Ar–P (6.4 V), as-clean (7.0 V) and H₂–P (7.2 V) plasma, respectively. The mechanisms behind the improved performance were proposed and discussed.     

High-performance diketopyrrolopyrrole-based organic field-effect transistors for flexible gas sensors

We demonstrate high-performance flexible polymer OFETs with P-29-DPP-SVS in various geometries. The mobilities of TG/BC OFETs are approximately 3.48 ± 0.93 cm²/V s on a glass substrate and 2.98 ± 0.19 cm²/V s on a PEN substrate. The flexible P-29-DPP-SVS OFETs exhibit excellent ambient and mechanical stabilities under a continuous bending stress of 1200 times at an R = 8.3 mm. In particular, the variation of μ_FET, V_Th and leakage current was very negligible (below 10%) after continuous bending stress. The BG/TC P-29-DPP-SVS OFETs on a PEN substrate applies to flexible NH₃ gas sensors. As the concentration of NH₃ increased, the channel resistance of P-29-DPP-SVS OFETs increased approximately 100 times from ∼10⁷ to ∼10⁹ Ω at V_SD = −5 V and V_GS = −5 V.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

Surface and interface characterization of oxygen plasma activated anodic bonding of glass–ceramics to stainless steel

The anodic bonding of RAS glass–ceramics to stainless steel were carried out at 350–400 °C and 800–1000 V under atmosphere, the micro-topography and compositions of the bonding interfaces also were investigated. With the assistant of oxygen plasma activated, anodic bonding was achieved at 350 °C and 800 V for 23 min under atmosphere, and the anodic bonding strength was up to 1.23 MPa. Experiments results pointed out oxygen plasma could help forming the bonding with glass–ceramics to stainless steel, and the width of cation depletion layer about 50 μm, lithium iron oxide (LiFe₅O₈ and Li₅FeO₄) were observed on the surface of glass–ceramics after anodic bonding.     

D–A copolymer with high ambipolar mobilities based on dithienothiophene and diketopyrrolopyrrole for polymer solar cells and organic field-effect transistors

Donor–acceptor (D–A) type conjugated polymers have been developed to absorb longer wavelength light in polymer solar cells (PSCs) and to achieve a high charge carrier mobility in organic field-effect transistors (OFETs). PDTDP, containing dithienothiophene (DTT) as the electron donor and diketopyrrolopyrrole (DPP) as the electron acceptor, was synthesized by stille polycondensation in order to achieve the advantages of D–A type conjugated polymers. The polymer showed optical band gaps of 1.44 and 1.42 eV in solution and in film, respectively, and a HOMO level of 5.09 eV. PDTDP and PC₇₁BM blends with 1,8-diiodooctane (DIO) exhibited improved performance in PSCs with a power conversion efficiency (PCE) of 4.45% under AM 1.5G irradiation. By investigating transmission electron microscopy (TEM), atomic force microscopy (AFM), and the light intensity dependence of J_SC and V_OC, we conclude that DIO acts as a processing additive that helps to form a nanoscale phase separation between donor and acceptor, resulting in an enhancement of μ_h and μ_e, which affects the J_SC, EQE, and PCE of PSCs. The charge carrier mobilities of PDTDP in OFETs were also investigated at various annealing temperatures and the polymer exhibited the highest hole and electron mobilities of 2.53 cm² V⁻¹ s⁻¹ at 250 °C and 0.36 cm² V⁻¹ s⁻¹ at 310 °C, respectively. XRD and AFM results demonstrated that the thermal annealing temperature had a critical effect on the changes in the crystallinity and morphology of the polymer. The low-voltage device was fabricated using high-k dielectric, P(VDF-TrFE) and P(VDF-TrFE-CTFE), and the carrier mobility of PDTDP was reached 0.1 cm² V⁻¹ s⁻¹ at V_d = −5 V. PDTDP complementary inverters were fabricated, and the high ambipolar characteristics of the polymer resulted in an output voltage gain of more than 25.     

Characteristics of ZnOV2O5MnO2Nb2O5Er2O3 semiconducting varistors with sintering processing

The effects of sintering temperature on the microstructure, electrical properties, and dielectric characteristics of ZnOV₂O₅MnO₂Nb₂O₅Er₂O₃ semiconducting varistors have been studied. With increase in sintering temperature the average grain size increased (4.5–9.5 μm) and the density decreased (5.56–5.45 g/cm³). The breakdown field decreased with an increase in the sintering temperature (6214–982 V/cm). The samples sintered at 900 °C exhibited remarkably high nonlinear coefficient (50). The donor concentration increased with an increase in the sintering temperature (0.60×10¹⁸–1.04×10¹⁸ cm^?3) and the barrier height exhibited the maximum value (1.15 eV) at 900 °C. As the sintering temperature increased, the apparent dielectric constant increased by more than four-fold.     

Low-voltage,high-performance n-channel organic thin-film transistors based on tantalum pentoxide insulator modified by polar polymers

Polar polymers (polyfluorene copolymers, PFN–PBT) with different polarities are utilized to modify the surface of tantalum pentoxide (Ta₂O₅) insulator in n-channel organic thin-film transistors (OTFTs). A high mobility of 0.55 cm²/Vs, high on/off current ratio of 1.7 × 10⁵, and low threshold voltage of 2.8 V are attained for the OTFT with the modification polymers, the performances of which are much better than those of OTFT with only Ta₂O₅ insulator. The performances of the OTFT with only Ta₂O₅ insulator are only 0.006 cm²/Vs in mobility, 5 × 10³ in on/off ratio, and 12.5 V in threshold voltage. Furthermore, it is found that the threshold voltage of the OTFTs with PFN–PBT modification layer is easily tuned by polarities of the polymers. Further studies show that self-assembly dipole moments in the polymers play an important role in the improvement of the OTFT performances.     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

A study of charge transport in a novel electroluminescent poly(phenylene vinylene-co-fluorenylene vinylene) based π-conjugated polymer

The charge transport properties in a novel electroluminescent poly{[2-(4′,5′-bis(3″-methylbutoxy)-2′-p-methoxy-phenyl)phenyl-1,4-phenylene vinylene]-co-(9,9-dioctyl-2,7-fluorenylene vinylene)} (BPPPV-PF) have been studied using a time-of-flight (TOF) photoconductivity technique. The TOF transients for holes were recorded over a range of temperatures (207–300 K) and electric fields (1.5 × 10⁵–6.1 × 10⁵ V/cm). The hole transport in this polymer was weakly dispersive in nature with a mobility at 300 K of 5 × 10⁻⁵ cm²/V s at 2.5 × 10⁵ V/cm. This increased to 8.4 × 10⁻⁵ cm²/V s at 6.1 × 10⁵ V/cm. The temperature and field dependence of charge mobility has been analyzed using the disorder formalisms (Bässler’s Gaussian disorder model (GDM) and correlated disorder model (CDM)). The fit with Gaussian disorder (GDM) model yielded the mobility pre-factor μ_∞ = 1.2 × 10⁻³ cm²/V s, energetic disorder parameter σ = 82 meV and positional disorder parameter Σ = 1.73. The average inter-site separation (a = 7 Å) and the charge localization length (L = 3.6 Å) was estimated by assuming the CDM type charge transport. The microscopic charge transport parameters derived for this polymer are almost identical to the reported values for fully conjugated polymers with high chemical purity. The results presented indicate that the charge transport parameters can be controlled and optimized for organic optoelectronic applications.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Bottom gate organic thin-film transistors fabricated by ultraviolet transfer embossing with improved device performance

Ultraviolet transfer embossing is optimized to fabricate bottom gate organic thin-film transistors (OTFTs) on flexible plastic substrates, achieving significant improved device performance (μ = 0.01–0.02cm²/Vs; on/off ratio = 10⁴) compared with the top gate OTFTs made previously by the same method (μ = 0.001–0.002 cm²/Vs; on/off ratio = 10²). The performance improvement can be ascribed to the reduced roughness of the dielectric-semiconductor interface (R_rms = 0.852 nm) and thermally cross-linked PVP dielectric which leads to reduced gate leakage current and transistor off current in the bottom-gated configuration. This technique brings an alternative great opportunity to the high-volume production of economic printable large-area OTFT-based flexible electronics and sensors.