双色红外焦平面数字读出电路研究

设计了一款中、长波双色应用的数字化红外焦平面读出电路。由于双色红外焦平面器件在注入电流及动态输出阻抗上存在着数量级的差异,同时双波段均要求高灵敏度,因此读出电路需要在有限像元面积内实现双输入级的结构设计和大动态范围。电路采用基于直接注入型输入级的脉冲频率调制结构,设计电荷复位单元代替传统电压复位结构,可降低可探测的电荷分辨率,并改善由复位遗失电荷带来的非线性影响,同时电路设计了20bit混合结构的计数器,满足电路大电荷容量和低功耗的要求。仿真结果表明,实现的最小电荷分辨率为692e-,对应电荷容量为7.2×10⁸e-,双波段探测线性度均高于99.8%,在中、长波典型应用情况下功耗分别为3.03,6.66μW。     

A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications

This paper presents a low-power wideband signaling (WBS) digital transceiver for data transmission through a human body for body area network applications. The low-power and highspeed human body communication (HBC) utilizes a digital transceiver chip based on WBS and adopts a direct-coupled interface (DCI) which uses an electrode of 50-Omega impedance. The channel investigation with the DCI identities an optimum channel bandwidth of 10 kHz to 100 MHz. The WBS digital transceiver exploits a direct digital transmitter and an all-digital clock and data recovery (CDR) circuit. To further reduce power consumption, the proposed CDR circuit incorporates a low-voltage digitally-controlled oscillator and a quadratic sampling technique. The WBS digital transceiver chip with a 0.25-mum standard CMOS technology has 2-Mb/s data rate at a bit error rate of 1.1 times 10^-7, dissipating only 0.2 mW from a 1-V supply generated by a 1.5-V battery.     

Digital MEMS for optical switching

Over the last few years an amazing amount of interest has emerged for applications of micro electro-mechanical systems (MEMS) in telecommunications. Silicon-based optical MEMS have proven to be the technology of choice for low-cost scalable photonic applications because they allow mass manufacturing of highly accurate miniaturized parts, and use materials with excellent mechanical and electrical properties. Applications include tunable lasers, optical switches, and tunable filters. The use of MEMS for optical switching has turned out to be most attractive since this application could revolutionize fiber optic telecommunications. We discuss the technology, performance, and reliability of 2D MEMS optical switches. We show that this technology meets the scalability, performance, and reliability requirements for important applications in fiber optic networks     

一种1.25 Gbps CMOS以太网串并/并串转换电路

用0．35μm CMOS工艺实现了单芯片1．25Gbps千兆以太网串并／并串转换电路。该电路兼容ANSI的光纤信道物理层标准(FC-0)。与同类电路相比，其核心单元—并串转换电路和串并转换电路—具有结构简单、面积小的优点[1，2]，其高速串行数据随机抖功只有同类电路的一半。另外，电路中还集成了锁相环环路滤波电容。     

一种用于DTV中A/V延时校正的数字水印嵌入技术

提出了一种把节目音频包络编码作为数字水印数据嵌入到视频信号中,以记录所需的A/V定时关系,并保持恒定和适当的A/V校正的软件处理方法.结果表明,本系统能在使用中提供实时的、全自动的A/V延时校正.与现有测定A/V延时的方法不同,它不存在干扰音频测试的随机噪声,也不需要中断实际节目的视频测试信号.     

5-bit 1.25GS/s Flash ADC的设计及数字后台校正的实现

-本文设计了一款高速的全并行模数转换器,并基于Volterra级数设计了校正反模型,对此款ADC进行了数字后台校正。首先,基于0.18 CMOS设计了一个采样频率为1.25GHz分辨率为5位的Flash ADC,该ADC采用分布式采保结构对输入信号进行量化。同时,基于Volterra级数,实现了数字后台校正模型的设计,并基于此模型对所设计的高速Flash ADC的非线性进行了补偿和校正。仿真结果表明,ADC的输出信号谐波得到了很好的抑制,当输入信号频率为117.1M时,有效位数达到了4.83bit;当输入信号接近奈奎斯特频率时,有效位数达到了4.74bit。     

A 1.25-gb/s burst-mode receiver for GPON applications

This paper presents a 1.25-Gb/s burst-mode receiver (BMRx) for upstream transmission over gigabit passive optical networks (G-PONs). The dc-coupled receiver uses a unique arrangement of three limiting amplifiers to convert the bursty input signal to a current mode logic output signal while rejecting the dc offset from a preceding transimpedance amplifier. Peak detectors extract a decision threshold from a sequence of 12 successive nonreturn-to-zero (NRZ) 1's and 12 successive NRZ 0's received at the beginning of each packet. Automatic compensation of the remaining offsets of the BMRx is performed digitally via digital-to-analog converters. The chip was designed in a 0.35-/spl mu/m SiGe BiCMOS process. The receiver contains an APD with a gain of 6 and a transimpedance amplifier and shows a sensitivity of -32.8 dBm and a dynamic range of 23.8 dB. A sensitivity penalty of 2.2 dB is incurred when a packet with average optical power of -9 dBm precedes the packet under consideration, the guard time between the packets being 25.6 ns. The BMRx includes activity detection circuitry, capable of quickly detecting average optical levels as low as -35.5 dBm. The performed measurements prove that the receiver meets the G-PON physical media dependent layer specification defined in ITU-T Recommendation G.984.2.     

一种红外焦平面读出电路数字模块的设计

介绍了一种红外焦平面读出电路数字模块的设计与实现。该模块可以提供系统正常工作所需的时序,包括行选列选、采样保持等。此外,该模块还可以进行输出模式的切换,实现多路输出,提高输出帧频。介绍了多路输出的Verilog算法、电路的整体结构和时序,并给出了整个系统的仿真结果。设计的模块采用华润上华CSMC 0.5μm DPTM单阱CMOS工艺流片成功,验证了设计的正确性。测试结果表明,对64×64的阵列,四路输出时,输出帧频可以达到240fps,可应用于车辆夜视领域。     

用于红外焦平面读出电路的新型输出缓冲器

根据红外焦平面读出电路输出缓冲器的大输出摆幅和大压摆率的特点,设计了一种应用于红外焦平面读出电路的新型输出缓冲器,由于输出缓冲器需要一个较大的输出摆幅,所以采用轨对轨输入以及AB类输出的全差分运放,使其在不损失增益的情况下提高带宽和输出摆幅;并在轨对轨结构中插入恒定跨导电路,使电路更加稳定;在输出缓冲器高压摆率的要求下...     

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm². The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns     

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 Voperation

This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-μm n-well CMOS process     

A 12-mW 6-bit video-frequency A/D converter

A 6-b 30-MHz flash A/D converter using 8.4-GHz cutoff frequency sidewall base contact structure (SICOS) technology is described. By using n-p-n transistors operated upwardly (in reverse-action condition) and p-n-p transistors with a 860-MHz cutoff frequency, a power consumption of 12 mW has been achieved, with a 3-V power supply. This converter can digitize video signals of up to 7 MHz at a conversion frequency of 30 MHz. An SNR of 37 dB was observed. Chip area of the fabricated converter is 1.5 mm/SUP 2/.     

开关线型四位数字MEMS移相器

介绍了一种基于射频微机械串联开关设计的开关线型四位数字微机电系统(M icro-e lectrom echan ica lSystem s以下简称M EM S)移相器。该移相器集成了16个RF M EM S开关,使用了13组四分之一波长传输线和M IM接地耦合电容,有效地使开关的驱动信号和微波信号隔离,串联容性开关设计有效地降低了开关的启动电压。使用低温表面微机械工艺在360μm厚的高阻硅衬底上制作移相器,芯片尺寸4.8 mm×7.8 mm。移相器样品在片测试结果表明,频点10.1 GH z,22.5°相移位的相移误差为±0.4,°插损2.8 dB;45°位的相移误差为±1.1,°插损2.0 dB;在X波段,对16个相移态的测试结果表明,移相器的插入损耗小于4.0 dB,驻波比小于2.4,开关驱动电压为17~20 V。     

A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5–bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.      

Implementation of the TDA Digital Mode on a ROIC for Scanning IR FPA

Journal of Communications Technology and Electronics - In this paper, we present the results of the development of a readout integrated circuit for scanning infrared focal plane arrays with digital...     

用于高速量子密码系统的1.25 GHz InGaAs/InP单光子探测器的研制

随着量子密码领域的快速发展,近红外单光子探测器的研究已经成为该领域的研究重点和技术制高点。报道了一种基于正弦门控与滤波技术的InGaAs/InP雪崩光电二极管(APD)高速单光子探测器,门控频率达到1.25GHz。在探测效率为10.3%时,暗计数概率为1.3×10-6/gate,后脉冲概率为5.6×10-5/ns。这种高速单光子探测器将大幅度提升量子密码系统的两个关键指标——密钥率和传输距离,为下一代高速量子密码系统的实用化应用奠定了基础。     

A 150-mW, 8-bit video-frequency A/D converter

The authors describe an 8-bit, extremely low-power, flash A/D converter LSI for video-frequency image signal processing. This converter uses a shallow-groove-isolated bipolar VLSI technology. It consumes only 150 mW, which is half the amount of the lowest power consumption so far reported. This low level of power consumption is achieved by the use of a comparator circuit, which is newly designed. This converter can digitize video signals of up to 10 MHz at a conversion rate of 30 MHz. A differential gain (DG) error of 1% and a differential phase (DP) error of less than 0.5/spl deg/ were observed.     

A 27-mW 3.6-gb/s I/O transceiver

This paper describes a 3.6-Gb/s 27-mW transceiver for chip-to-chip applications. A voltage-mode transmitter is proposed that equalizes the channel while maintaining impedance matching. A comparator is proposed that achieves sampling bandwidth control and offset compensation. A novel timing recovery circuit controls the phase by mismatching the current in the charge pump. The architecture maintains high signal integrity while each port consumes only 7.5 mW/Gb/s. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.     

基于MEMS加速度计的单轴数字倾角传感器

在分析MEMS加速度传感器测量倾角的原理和方法的基础上,设计了基于MEMS双轴加速度传感器的数字化全量程单轴倾角传感器,并介绍了其软硬件实现。通过分析加速度传感器的安装误差及X轴和Y轴的灵敏度差异,给出了加速度传感器的参数校正算法,并确定合适的测量频率与带宽,经测试,所设计的数字化单轴倾角传感器测量范围±180°,精度0.1°。     

A 56-mW 23-mm/sup 2/ single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm/sup 2/ radio

A 56-mW 23-mm/sup 2/ GPS receiver with CPU-DSP-64 kRAM-256 kROM and a 27.2-mW 4.1-mm/sup 2/ radio has been integrated in a 180-nm CMOS process. The SoC GPS receiver, connected to an active antenna, provides latitude, longitude, height with 3-m rms precision with no need of external host processor in a [-40, 105]/spl deg/C temperature range. The radio draws 17 mA from a 1.6-1.8-V voltage supply, takes 11 pins of a VFQFPN68 package, and needs just a few passives for input match and a crystal for the reference oscillator. Measured radio performances are NF=4.8 dB, Gp=92 dB, image rejection > 30 dB, -112 dBc/Hz phase noise @ 1 MHz offset from carrier. Though GPS radio linearity and ruggedness have been made compatible with the co-existence of a microprocessor, radio silicon area and power consumption is comparable to state-of-the-art stand-alone GPS radio. The one reported here is the first ever single-chip GPS receiver requiring no external host to achieve satellite tracking and position fix with a total die area of 23 mm/sup 2/ and 56-mW power consumption.