A method for locating the position of oxide traps responsible forrandom telegraph signals in submicron MOSFETs

Random telegraph signals (RTS) have been measured in the drain to source voltage of W×L=0.97×0.15 μm² medium-doped drain (MDD) n-MOSFET's. The depth of the trapping center in the oxide is found from the gate voltage dependence of the emission and capture times. The difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes is utilized to find the position of the trap in the channel with respect to the source     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

Analysis of slow traps centres in submicron MOSFETs by random telegraph signal technique

In this paper, we present a comprehensive study of slow single traps, situated inside the gate oxide of small area (W×L=0.5×0.1 μm²) metal–oxide–semiconductor (MOS) transistors. The gate oxide of the analyzed transistors, which have been used for memory-cell applications, is composed of two SiO₂ layers—a deposited high-temperature oxide (HTO) and the thermal oxide. The interface between the two gate oxides is shown to play a significant role in the channel conduction: we observed that the presence of individual traps situated inside the gate oxide, at some angstroms from the interface with the channel, is inducing discrete variations in the drain current. Using random telegraph signal (RTS) analysis, for various temperatures and gate bias, we have determined the characteristics of these single traps: the energy position within the silicon bandgap, capture cross section and the position within the gate oxide.     

Characterization of a 0.13 μm CMOS Link Chip using Time Resolved Emission (TRE)

The Picosecond Imaging Circuit Analysis (PICA) technique using the Superconducting Single-Photon Detector (SSPD) allows the detailed characterization of pulse width variations along the delay chain of a high speed Self Timing Interface (STI). Pulses gradually shrink and finally disappear along the delay chain.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Static and low frequency noise characterization of surface- and buried-mode 0.1 μm P and N MOSFETs

This work presents the low frequency noise and the electric performances in terms of output/transfer characteristics, threshold voltage, and short channel effect in both NMOS and PMOS transistors for 0.1 μm technologies. For the last one there are two architectures based either on a surface mode of operation (surface channel) or on a buried one (buried channel) featuring either a P+ or a N+ polysilicon gate material. The impact of the channel length on the noise characteristics as well as on the output/transfer characteristics is studied. We find that the 1/f noise can be interpreted in terms of carrier number fluctuations for both N and P channel MOSFETs for surface and buried mode of operation. The oxide trap density Nt is therefore evaluated, demonstrating an overall good oxide quality.     

Integration challenges in sub-0.25 μm CMOS-based technologies

Market demands, which require increased functionality at lower costs are driving the development of high performance CMOS technologies with very high integration density. These demands are pushing the continuous scaling down of technologies and are resulting in a progressive acceleration of the rate of introduction of new technology generations.Current research and development activities in CMOS technology are focused on scaling CMOS technologies below 0.25 μm dimensions. While some of the process modules can be scaled down in a conventional way, in some cases severe limitations are reached and it is necessary to introduce major modifications to the process flow.In this paper we will present an overview of the main considerations to be kept in mind when scaling down to a 0.18 or 0.13 μm CMOS technology generation.     

Electromigration in fine-line conductors (0.45–2 μm)

The electromigration behaviour of various metallization systems has been tested on Si, GaAs and GaInAs substrates. Lifetime dependence on temperature and current density has been measured by accelerated lifetime tests. Linewidth was between 0.45 μm and 2 μm. The best electromigration resistance was found for electroplated gold lines, however also the system Al on Ti showed a as much as 40 times better performance than standard Al metallization. For linewidths of 0.45 μm a steep increase in stability has been found.     

Interface traps and random dopants induced characteristic fluctuations in emerging MOSFETs

In this work, we study the effect of interface traps (ITs) and random dopants (RDs) on characteristics of 16-nm MOSFETs. Totally random generated devices with 2D ITs between the interface of silicon and HfO₂ film as well as 3D RDs inside the silicon channel are simulated. Fluctuations of threshold voltage and on/off state current for devices with different EOT of insulator film are analyzed and discussed. The results of this study indicate ITs and RDs statistically correlate to each other and RDs govern device variability, compared with the influence of ITs. Notably, the position of ITs and RDs induces rather different fluctuation in spite of the same number of ITs and RDs are investigated.     

Optical proximity correction for 0.3 μm i-line lithography

In printing random logic circuits down to 0.3 μm using i-line lithography, optical proximity correction is required to maintain across-the-chip linewidth uniformity. Using a rule-based approach with parametric anchoring, process characterization time is kept to a minimum. Corrections are more effective if post-OPC design grid sizes are kept small (5 nm at 1X).     

W‐Band MMIC chipset in 0.1‐μm mHEMT technology

We developed a 0.1‐μm metamorphic high electron mobility transistor and fabricated a W‐band monolithic microwave integrated circuit chipset with our in‐house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz–108 GHz band and achieved excellent spurious suppression. A low‐noise amplifier (LNA) with a four‐stage single‐ended architecture using a common‐source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W‐band image‐rejection mixer (IRM) with an external off‐chip coupler was also designed. The IRM provided a conversion gain of 13 dB–17 dB for RF frequencies of 80 GHz–110 GHz and image‐rejection ratios of 17 dB–19 dB for RF frequencies of 93 GHz–100 GHz.     

Photoluminescence beyond 1.5 μm from InAs quantum dots

Photoluminescence measurements were carried out to investigate the origin of long wavelength emissions (1.6 μm at room temperature) observed from wafers with InAs quantum dots capped with GaAsSb layers. For wafers with high Sb content (22% and 26%) photoluminescence peak energies were found to be linearly proportional to third root of optical excitation power, a characteristic of emission due to a type-II band alignment. This work therefore presents unambiguous evidence that the long wavelength emission of the wafers comes from type-II band alignment between the InAs quantum dots and the GaAsSb capping layers.     

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF₂ is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.     

Transformer coupled plasma dielectric etch for 0.25 μm technologies

Manufacturable etch processes for 0.18 μm technology TEOS bi-level contacts and vias (TEOS or TEOS/FOX/TEOS) are demonstrated in a low pressure high density reactor. Good CD control and high yields are demonstrated for structures down to 0.25 μm. In the process regimes used, the photoresist etch rate and the selectivity to underlayer are correlated with the amount of free fluorine in the plasma. The same TCP 9100 reactor can be used for low k polymer (Silk™ from Dow Chemical) etching with in situ hardmask open. A compromise between hard mask facetting and bowing has to be made unless passivating gases are added to an O₂/N₂ chemistry. For several architectures, initial results show potential integration with Cu.     

Open contact analysis of single bit failure in 0.18 μm technology

Single bit failure is the most common failure mode in static random access memory. Although a failing cell can be easily localized with bitmap data, the exact defect location within the failing cell cannot be found immediately, especially when a defect is related to contact. In this paper, a technique of contact-level passive voltage contrast has been proposed to detect such defects for a single bit failure. After an open contact was identified, subsequent transmission electron microscope analysis was performed and it was found that the root cause for the open contact was poly residue.     

Three-dimensional FEM simulations of thermomechanical stresses in 1.55 μm Laser modules

The purpose of this study is to present three-dimensional simulations using finite element method (FEM) of thermomechanical stresses and strains in 1550 nm Laser modules induced by Nd:YAG crystal Laser welds and thermal cycles on two main sub-assemblies: Laser submount and pigtail. Non-linear FEM computations, taking into account of experimental σ() measured curves, show that Laser welding process can induce high level of strains in columns of the Laser platform, bearing the Laser diode, responsible of an optical axis shift and a gradual drop of the optical power in relation with relaxation of accumulated stresses in the sub-assembly. In the case of thermal cycles, stresses can occur on elements sensitive to coefficient of thermal expansion mismatches such as solder joint between the Laser platform and thermoelectric cooler and as fiber glued into the pigtail leading to crack propagation with sudden drop of optical power. The main objective of the paper is to evaluate thermomechanical sensitivity and critical zones of the Laser module in order to improve mechanical stability after Laser weld and reach qualification standards requirements without failures. Experimental analyses were also conducted to correlate simulation results and monitor the output optical power of Laser modules after 500 thermal cycles (−40 °C/+85 °C VRT).     

TLP analysis of 0.125 μm CMOS ESD input protection circuit

In this investigation, TLP ESD analysis shows that if a large input resistor is used in combination with a secondary ggNMOS clamp in the input protection circuitry, then the trigger voltage, V_t1, of the ggNMOS clamp is not a constant. The value is influenced by the size and properties of the input resistor, by current injection problems due to parallel resistive networks formed between the primary and secondary ESD circuits, by reverse bias diode leakage currents effects, and by source elevation effects due to voltage rises along the ESD ground bus.     

Reliability of 80 μm pitch flip chip attachment on flex

The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.     

Development of substrate-pumped nMOS protection for a 0.13 μm technology

A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complemented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time. HBM data that shows the substrate-pumped nMOS can provide dramatically higher protection than estimated from conventional I_t2 measurements. This motivates improved ESD circuit development. The nMOS clamp transistor is characterized as an actively biased LNPN, which is how it is used in a substrate-pumped protection circuit. A systematic approach to circuit development is described that is based upon empirical characterization of well-defined circuit components under conditions approximating ESD.