容错系统中的自校验技术及实现方法

阐述了自校验技术在容错系统中的作用，给出了自校验网络实现原理及实现方法，指出用VHDL语言结合FPGA／CPLD是实现大规模自校验网络的有效途径。     

数字电路并发差错检测的新概念

并发差错检测是提高数字电路与系统可信的重要技术。文中建立了一种基于并发差错检测电路的结构模型。它由实现电路基本功能的基本功能模块和实现电路并发差错检测功能的检测器部分联所构成;提出了表征基于部分自校验概念的并发差错检测机制的一组新概念：精简强故障保险、精简强变量分离、精简强自校验、ｋ－容错精简强故障保险、ｋ－容错精简强变量分离和ｋ－容错精简强自校验,并研究了数字电路并发差错检测的主要概念之间的关系     

利用固定字段的自同步加扰系统容错译码

香农指出,信源中的冗余可以在接收端被用来提高系统性能。固定字段可以看作是信源中的冗余。本文研究自同步加扰系统信源固定字段利用问题,提出由去扰数据进行固定字段检测,得出错误位置,并进一步映射为去扰前错误位置,从而在译码之前预先纠错的容错处理方法。由于容错后的数据流恢复了部分错误,误码率得到降低,因此译码结果明显改善。仿真结果显示,当信源载荷率为30%时,通过利用固定字段,容错译码可获得0.5dB左右的信噪比增益。     

三余度飞控计算机关键技术研究及工程实现

针对小型飞行器飞控计算机可靠性指标要求,介绍了运用余度技术提高其可靠性与容错能力的方法,提出了采用三余度技术保证飞控计算机可靠性的设计方案,通过选择合适的冗余模式,建立了三余度飞控计算机的架构模型,经过详细分析与研究各模块结构,给出了余度策略、同步算法、表决面选取等关键技术工程实现的硬件电路与软件流程,仿真验证与试验结果表明,该方案设计合理,不仅较好地完成了飞控计算机的余度管理任务,而且有效地保证了系统的可靠性与容错能力。     

交替互补定位器及其用于双模比较冗余结构的差错定位

双模比较冗余结构是一种广泛应用的低成本容错结构。当两个冗余模块之一发生故障时,比较器将给出差错检测指示输出,该输出既可以按中断信号形式通知系统作出相应的差错处理,也可以按硬件信号形式直接用于终止系统工作或启动重构,目的是防止故障冗余结构给出错误输出,或者确保系统能够提供连续的服务。这种冗余结构的缺点是比较器不能确切指明故障模块,并因此而需要较大的时间开销来完成系统重构和恢复操作。为解决这一问题,提出了一种具有并发输出差错定位功能的双重比较冗余结构。其中单个冗余模块的输出是一个交替矢量,两个冗余模块的输出形成了一个交替互补矢量,该矢量送入一个交替互补定位器。在正常输入情况下,根据定位器的输出就可以确定冗余系统是无差错的、还是冗余模块或定位顺本身存在故障。交替互补定位器由D型触发器和通用门电路构成,它被证明为是一个完全故障定位的定位器。由于所提出的双模比较冗余结构是基于时间冗余原理工作的,因此它适用于对速度要求并不是非常苛刻的容错系统。     

浅议CRC算法在计算机网络通信中应用

在计算机网络通信中,为了把信息及时可靠地传送给对方,通信系统都采用了差错控制。循环冗余校验(Cyclic Redundancy Check)就是一种被广泛采用的错误检验编码,本文介绍了循环冗余校验算法的原理、循环冗余校验算法分析、循环冗余校验算法设计,简称CRC。     

逻辑值冗余的一种实现方案——三中取二值自校验逻辑系统

逻辑值冗余是指用n值逻辑电路构成m值逻辑系统,其中n>m。此时有(n-m)个逻辑值是冗余的;但它们可以被用来产生自校验、纠错等功能,以提高系统的可测试性及可靠性。本文提出逻辑值冗余的一种实现方案——三中取二值自校验逻辑系统。这种系统是逻辑值冗余在n=3,m=2时的特例。本文内容包括三中取二值逻辑算子及自校验定义、三中取二值组合系统及三中取二值同步时序系统等。     

浅析CRC

什么是CRCCRC是“CyclicRedundancyCheck”的缩写，它的中文意思是“循环冗余校验”。如同我们熟知的奇偶校验一样，这是一种用于检测数据在传输过程中有无错误的方法，不过它的校验能力比奇偶校验不知要强多少倍。一个构造得很好的CRC码生成多项式能够10O％地检测出一位错、双位错、奇数位错；能够100％地检测出长度小于等于信息位长度的阶的突发性错误等等。它是一种高效的校验手段，因此微机系统的软盘和硬盘在传输数据时几乎全部使用CRC来作校验。CRC检验原理我们可以将传输的信息看作是一个多项式的系数。例如；ASCll码“A”…     

Modbus通信协议中CRC校验的快速C语言算法

本文主要讨论了Modbus通信协议的RTU帧格式中常用的错误校验方法,即循环冗余校验法(CRC)。提出了Modbus协议反转CRC校验的方法,推导了反转CRC校验快速计算表格,并用C语言实现了基于快速查表算法的循环冗余校验程序。     

起落架多冗余度收放控制器设计

起落架收放系统对大型客机的安全性至关重要,其中起落架收放控制和指示子系统的安全性以及指示的正确性,对减少故障的发生和提高维修性具有重要意义。文中设计了一种采用双-双余度结构的起落架收放控制器,将有中心裁决冗余与无中心裁决冗余相结合,并同时采用了非相似余度设计以及各种软硬件错误检测,极大地提高了系统的可靠性,实际运行证明此设计是十分可靠的。     

Self-checking circuits and decoding algorithms for binary hamming and BCH codes and Reed-Solomon codes over GF(2 m )

We consider problems of detecting errors in combinational circuits and algorithms for the decoding of linear codes. We show that a totally self-checking combinatorial circuit for the decoding of a binary Hamming [n, k] code can be constructed if and only if n = 2 ^r ? 1, r = n?k. We introduce the notion of a totally self-checking combinational circuit detecting error clusters of size at most µ; for shortened Hamming [n,k] codes, we construct totally self-checking decoding combinational circuits detecting error clusters of size at most µ, 2 ≤ µ < n?k. We describe single-error protected and self-checking algorithms: the extended Euclidean algorithm and decoding algorithms for binary BCH codes and Reed-Solomon codes over GF(2 ^m ).     

Embedded totally self-checking checkers: a practical design

In a totally self-checking (TSC) design, the circuit detects errors by monitoring redundantly coded data/control paths through a TSC checker. A problem arises when not all these code words are on the monitored lines during normal operation. A method of designing checkers that solves this difficulty is proposed. The method uses TSC checkers based on flip-flops instead of using the mostly combinational checkers now available. Two design applications are presented: TSC checkers for arithmetic AN codes, and a TSC iterative logic array     

1/3码的动态CMOS全自检电路的设计

自检测电路设计方法有多种多样,本文中介绍了TSC电路的概念,并采用1/3码的动态CMOS设计TSC电路,通过在Cadence环境下仿真,仿真结果表明本设计可行。     

基于敏感寄存器替换的电路软错误率与开销最优化

随着集成电路的发展,逻辑电路对放射性粒子引起的软错误越来越敏感.现有的电路加固技术通常会带来较大的面积开销.综合考虑电路的软错误率和面积开销,提出一种新的电路加固评估指标FAP,并提出基于贪婪算法的寄存器替换技术,通过将电路的部分敏感寄存器替换为冗余寄存器来免疫电路中的软错误.针对贪婪算法有时不能达到可靠性和开销整体最优的局限,进一步提出可靠性-开销最优的启发式替换算法.实验结果表明,基于贪婪算法的寄存器替换技术只需50%的面积开销就可降低90%的电路软错误率;而可靠性-开销最优的启发式替换算法只需45%左右的面积开销,电路软错误率就降低达90%以上.与其他已有技术相比,电路软错误免疫技术在可靠性和面积开销间达到了更好的折中.     

应用模逆运算的移动互联网可信终端设计方法

针对移动互联网海量移动终端用户的可信接人问题提出了一种芯片加密的可信接人系统的设计方案。首先将移动终端的可信接人过程划分为硬件预处理和可信接入两个子系统;在硬件预处理部分将有限状态机的思想用于模逆运算电路控制子系统的状态描述;而在可信接入部分基于Verilog语言将模拟运算电路抽象为控制系统状态转移图,再运用Verilog语言中的always模块将其转换为Moore型有限状态机,同时采用寄存器同步稳定输出控制信号,有效地实现了移动互联网终端设备的可信接入问题。仿真实验表明文中方法不仅能实现控制信号的输出与状态同步,还能避免组合输出产生的延迟及竞争与冒险现象,使终端设备的接入过程更加高效、稳定和可靠。     

Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger’s code

We formulate necessary and sufficient conditions for detecting a fault at the output of a logical element in a combination logical device in a concurrent error-detection system based on Berger’s code. We introduce the notion of a fully testable fault. We show that in order to ensure that all single faults in combination devices are detected with their concurrent checking based on Berger’s code we can use not only the property that it detects 100% of unidirectional errors but also the property that it detects 100% of asymmetrical errors. Due to the latter property, we can reduce structural redundancy of the combination device, when transforming its circuit to one amenable for control, compared to known algorithms for modifying the structure of combination devices into circuits with unidirectionally independent outputs.     

Evolutionary design of complex approximate combinational circuits

Functional approximation is one of the methods allowing designers to approximate circuits at the level of logic behavior. By introducing a suitable functional approximation, power consumption, area or delay of a circuit can be reduced if some errors are acceptable in a particular application. As the error quantification is usually based on an arithmetic error metric in existing approximation methods, these methods are primarily suitable for the approximation of arithmetic and signal processing circuits. This paper deals with the approximation of general logic (such as pattern matching circuits and complex encoders) in which no additional information is usually available to establish a suitable error metric and hence the error of approximation is expressed in terms of Hamming distance between the output values produced by a candidate approximate circuit and the accurate circuit. We propose a circuit approximation method based on Cartesian genetic programming in which gate-level circuits are internally represented using directed acyclic graphs. In order to eliminate the well-known scalability problems of evolutionary circuit design, the error of approximation is determined by binary decision diagrams. The method is analyzed in terms of computational time and quality of approximation. It is able to deliver detailed Pareto fronts showing various compromises between the area, delay and error. Results are presented for 16 circuits (with 27–50 inputs) that are too complex to be approximated by means of existing evolutionary circuit design methods.     

Testing And Applications of Inverter-Free PLAs

The testing properties of inverter-free PLAs make them ideal for application to totally self-checking and easily testable circuits. After a class of test patterns and masking relations for these new patterns are determined, a complete test set for single and multiple crosspoint faults can be easily generated. Moreover, the procedure does not require any fault simulation. The code space inputs detect all single and multiple faults in PLAs for totally self-checking circuits, even if the faults are not unidirectional. The test results can be used to analyze easily testable PLAs. With minor hardware changes in one-input decoder PLAs, the personality matrix will serve as a complete test set.     

Dependable design technique for system-on-chip

A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters.