Design techniques for low-voltage high-speed pseudo-differential CMOS track-and-hold circuit with low hold pedestal

A low-voltage pseudo-differential double-sampled track-and-hold circuit with low hold pedestal based on the Miller-effect scheme is proposed. Rail-to-rail operation of bootstrapped switches allows the low-voltage T/H circuit implementation. Simulation results confirm that the proposed circuit is effective in low-voltage applications with low hold pedestal.     

Class AB CMOS analogue squarer circuit

CMOS analogue squarer circuit is presented. A compact pseudo-differential pair insensitive to input common-mode variations leads to class AB operation, hence yielding dynamic currents not bounded by quiescent currents. Measurement results for a 0.5 mum CMOS prototype are provided that verify the correct operation of the circuit.     

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.     

Low-jitter phase-locked loop based on pseudo-differential delayelements

A phase-locked loop (PLL) that is highly robust to supply/substrate noise is described. A new type of voltage-controlled oscillator (VCO) based on pseudo-differential delay elements is presented. The proposed circuit is implemented using a 0.35 μm CMOS process technology with a 3.3 V supply. It generates 16 clock phases at 250 MHz, tailored to gigabit link applications     

A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range

A new operational transconductance amplifier and capacitor based sinusoidal voltage controlled oscillator is presented. The transconductor uses two cross-coupled class-AB pseudo-differential pairs biased by a flipped voltage follower, and it exhibits a wide transconductance range with low power consumption and high linearity. The oscillator has been fabricated in a standard 0.8-/spl mu/m CMOS process. Experimental results show a frequency tuning range from 1 to 25 MHz. The amplitude is controlled by the transconductor nonlinear characteristic. The circuit is operated at 2-V supply voltage with only 1.58 mW of maximum quiescent power consumption.     

基于混合结构的一种高性能90nm CMOS逐次逼近A/D转换器

实现了一种10位2.5MS/s逐次逼近A/D转换器。在电路设计上采用了R-C混合结构D/A转换、伪差分比较结构以及低功耗电平转换方式实现。为了实现好的匹配性能,在版图布局上分别采用电阻梯伪电阻包围对策以及电容阵列共中心对称布局方式进行布局。整个A/D转换器基于90nm CMOS工艺实现,在3.3V模拟电源电压以及1.0V数字电源电压下,测得的DNL和INL分别为0.36LSB和0.69LSB。在采样频率为2.5MS/s,输入频率为1.2MHz时,测得的SFDR和ENOB分别为72.86dB和9.43bits。包括输出驱动在内,测得整个转换器的功耗为6.62mW。整个转换器的面积约为238um×214um。设计结果显示该转换器性能良好,非常适合多电源嵌入式SoC的应用。     

一种伪差分两级环形振荡器的设计

设计了一种伪差分两级环形振荡器,可为锁相环提供8 GHz四相位正交时钟。通过分析耦合两级环形振荡线性模型,对四级环形振荡结构进行优化,提出了伪差分两级环形振荡结构。基于单级缓冲器的开环分析,可对振荡器的输出频率进行精准估算,并判断振荡情况。采用65 nm CMOS工艺进行设计与仿真。结果表明,在1.2 V电压下,振荡器的功耗为6.9 mW,1 MHz频率处的相位噪声为－82.104 5 dB,满足高速SerDes接口的设计要求。     

A CMOS inverter-based class-AB pseudo-differential amplifier with current-mode common-mode feedback (CMFB)

This paper presents a CMOS inverter-based class-AB pseudo-differential amplifier comprising current-mode common-mode feedback (CMFB). The circuit employs two CMOS inverters and the complementary CMFB consisting of current-mode common-mode (CM) detector and transimpedance amplifier. The circuit has been designed using 0.18 μm CMOS technology and operates at 1 V supply. The simulation results demonstrate rail-to-rail operation with low CM gain (?15 dB). The power dissipation of the circuit is 102.5 μW.     

一种可编程高线性CMOSOTA的设计

采用SMIC 0.18 μm工艺,±0.9 V电源电压,提出了一种可编程高线性全对称伪差分 CMOS OTA 电路.提出的伪差 分输入级电路基于基本伪差分(PD)结构并采用 HD3 前馈技术消除三阶谐波失真,输出级采用可编程电流放大器实现.使用 Cadence 软件的 Spectre 仿真器进行电路仿真可得,Gm值三个...     

A pseudo-differential MDAC with a gain-boosting inverter for pipelined ADCs

In this paper, a power-efficient pseudo-differential (PD) multiplying digital-to-analog converter (MDAC) is presented for pipelined analog-to-digital converters (ADCs). The proposed MDAC eliminates the explicit common-mode feedback circuit which is required in fully-differential configurations without any power penalty. Furthermore, a new class-AB gain-boosting inverter is proposed to be used in PD MDAC structures for further power saving. This inverter provides dynamic load current with no significant static power consumption and achieves high DC gain using a new gain-boosting technique. To demonstrate the effectiveness of the proposed circuits, they are utilized in the realization of a 1.5-bit/stage 10 bit 100 MS/s pipelined ADC.     

一种新型的超低THD,低功耗CMOS音频功率放大器

提出了一种新型的系统矫正结构CMOS音频功率放大器.该放大器是由4个单端运放组成的伪差分结构.相对于传统的CMOS功率放大器,它具有低功耗、超低THD、易于补偿、驱动能力强等优点.采用1st silicon0.25μm 1P4M工艺制备,在3V电源电压下,驱动8Ω‖ 300pF的负载,其输出摆幅可以达到4Vpp,静态功耗小于3mW.在1kHz的正弦波激励下,其THD小于0.003%.还提出了一种新型的过流保护电路,可以对片内大功率输出级电路进行有效的保护.     

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.     

基于SiGe BiCMOS工艺的25Gbit/s跨阻放大器设计

采用0.25 μm SiGe双极CMOS (BiCMOS)工艺设计并实现了一种传输速率为25 Gbit/s的高速跨阻前置放大器(TIA).在寄生电容为65fF的情况下,电路分为主放大器模块、两级差分模块和输出缓冲模块.相比传统的跨阻放大器,TIA采用Dummy形式实现了一种伪差分的输入,减小了共模噪声,提高了电路的稳定性;在差分级加入了电容简并技术,有效地提高了跨阻放大器的带宽;在各级之间引入了射极跟随器,减小了前后级之间的影响,改善了电路的频域特性.电路整体采用了差分结构,抑制了电源噪声和衬底噪声.仿真结果表明跨阻放大器的增益为63.6 dBQ,带宽可达20.4 GHz,灵敏度为-18.2 dBm,最大输出电压为260 mV,功耗为82 mW.     

An E-band CMOS frequency quadrupler with 1.7-dBm output power and 45-dB fundamental suppression

This paper presents an E-band frequency quadrupler in 40-nm CMOS technology. The circuit employs two push–push frequency doublers and two single-stage neutralized amplifiers. The pseudo-differential class-B biased cascode topology is adopted for the frequency doubler, which improves the reverse isolation and the conversion gain. Neutralization technique is applied to increase the stability and the power gain of the amplifiers simultaneously. The stacked transformers are used for single-ended-to-differential transformation as well as output bandpass filtering. The output bandpass filter enhances the 4th-harmonic output power, while rejecting the undesired harmonics, especially the 2nd harmonic. The core chip is 0.23 mm² in size and consumes 34 mW. The measured 4th harmonic achieves a maximum output power of 1.7 dBm with a peak conversion gain of 3.4 dB at 76 GHz. The fundamental and 2nd-harmonic suppressions of over 45 and 20 dB are achieved for the spectrum from 74 to 82 GHz, respectively.     

A power-efficient 14.8-GHz CMOS programmable frequency divider with quadrature outputs in 40-nm CMOS process

This paper presents a power-efficient CMOS frequency divider (FD) with wide-band programmable division ratio and quadrature outputs for high-speed data transmission applications. The proposed FD consists of a power-efficient programmable divider (PD), a complementary volt-age-to-time converter based duty-cycle correction circuit, and a compact quadrature divider (QD). In the chain of PD, a sense-amplifier based dynamic flip-flop is proposed for 2/3 divider cell to achieve high-speed operation with significantly reduced power consumption. In addition, a simple but effective QD based on two pseudo-differential voltage-controlled tri-state inverters, is beneficial for generating precise quadrature output signals. Measurement results in 40-nm CMOS process show that the proposed FD achieves a wide division range from 16 to 254 and operates up to 14.8 GHz while consuming the power of 540.6 μW at 1.1-V supply, and occupying the active area of 0.00267 mm² (114.6 μm × 23.3 μm).     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

CMOS filter with wide digitally programmable VHF range

A novel approach is presented for programmable filtering over the VHF range based on fully-balanced pseudo-differential continuous-time transconductors for applications in low-voltage systems. An example third-order G_m-C lowpass Butterworth filter using the proposed transconductor and accumulation MOS capacitors has been implemented using an AMS 0.35 mum CMOS process, achieving -3 dB cutoff frequencies ranging from 40 to 200 MHz. The active chip area is 0.06 mm ² per pole     

Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps

This paper presents several comprehensive and novel circuit techniques that can be efficiently applied to low-voltage (LV) high-speed reset-opamp (RO) and switched-opamp (SO) in LV switched-capacitor circuits. The first, designated as virtual-ground common-mode (CM) feedback with output CM error correction, allows the design of fully differential RO circuits that could only be traditionally implemented before in pseudo-differential mode, and it leads to considerable savings of half of the opamps' power. The second, uses a crossed-coupled passive sampling interface to avoid the extra track-and-reset stages as required in both RO and SO circuits, further saving one front-end opamp's power. The third, employs a voltage-controlled level-shifting (LS) technique that utilizes the charge redistribution property to process the CM LS in an LV environment, avoiding the degradation of the feedback factor by the use of extra LS circuits. Finally, the fourth, the LV finite-gain compensation technique allows the use of low-gain high-speed single-stage amplifier in contrast to the conventional high-gain, low-speed two-stage opamp to achieve a high-speed operation in both RO and SO circuits. Without any clock boosting or bootstrap circuits, all of the above techniques can be applied in LV applications without any floating switches limitations. Measurement results of a 1.2-V 10-bit 60 MS/s pipelined analog–digital converter in 0.18- $mu$m CMOS with RO are presented to verify the effectiveness of the proposed techniques, achieving a signal-to-noise distortion ratio of 55.2 dB with 85-mW power consumption.      

一种用于TDC的低功耗多相时钟生成电路北大核心

在无人机3D地形测绘中，作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量，文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器，通过优化交叉耦合结构，在保证低功耗的前提下，提升了信号边缘的斜率，增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中，通过对环路带宽的考量选取了极低的偏置电流，在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明，在400 MHz的输出频率下，环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度，相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。     

超过100dB SFDR的1．2V14位20M采样保持放大器

设计了适用于14位20M流水线型模数转换器的采样保持电路.该电路采用了伪差分嵌套增益增强CMOS运算放大器,该运放的增益在各个corner及温度下都高于130dB,从而保证了采样保持电路的精度.在TSMC 0.13μm CMOS工艺下,仿真结果显示,该采样保持电路能够达到高于100dB的SFDR,完全满足14位的精度要求.