XAFS Investigation of Nanoparticle Formation in 64Zn+ Ion Implanted and Thermo Oxidized Si

Semiconductors - The single crystal CZ n-Si(100) substrates with electron concentration no = 5 × 1016 cm−3 were implanted by 64Zn+ ions with dose of 5 × 1016 cm−2 and energy...     

HgCdTe/CdTe heterostructure diodes and mosaics

This paper discusses the results of a study of the properties of HgCdTe/CdTe heterostructure diodes and mosaics. In this study, p-type HgCdTe epi-layers on the order of 20 µm were grown on CdTe substrates by a liquid-phase epitaxial (LPE) technique. These layers normally had a carrier concentration of 5 × 10¹⁶/cm³and a mobility of 400 cm²/V . s at 77 K. The n⁺-p junction was formed by boron ion implantation, and standard photolithographic techniques were used for the device fabrication. The diodes with no antireflection coating had a typical quantum efficiency of 40 percent. The 1/fnoise knee was on the order of 10 Hz at zero bias. Surface leakage seemed to be the dominant component for diodes at temperatures less than 77 K. From mosaic studies, it was found that the spectral spread was less than ±0.3 µm for an area as large as 12 × 20 mm. The study indicates that LPE offers a viable technique for producing high-quality HgCdTe epi-layers on CdTe.     

Increased oxygen precipitation in CZ silicon wafers covered by polysilicon

Increased oxygen precipitation in CZ silicon wafers covered by a polysilicon layer has been observed after a high temperature anneal. This study established that the low temperature anneal, inherent in the LPCVD polysilicon deposition process, is so responsible for the enhanced oxygen precipitation effect. Temperature-time parameters were developed to match oxygen concentration in the wafer material with preannealing (polysilicon deposition) temperatures to achieve various degrees of oxygen precipitation. Data from this work show that interstitial oxygen reduction (δ C_ox) saturation can be achieved after 100 min oxidation at 1150°C, if the polysilicon deposition temperature is between 670–700°C (150 min for a 1.3 Μm polysilicon layer) and the interstitial oxygen concentration in the wafer is between 22 and 24 ppm. A denuded zone of 20 Μm was obtained and can be observed on a chemically etched cross section. Chemically etched and decorated defects in these samples with various degrees of oxygen precipitation are also displayed in these optical micrographs.     

Laser-recrystallized polycrystalline-silicon thin-film transistors with low leakage current and high switching ratio

Laser-recrystallized polycrystalline-silicon thin-film transistors (poly-Si TFT's) with offset-gate structures have been fabricated on quartz substrates. Offset-gate structures make it possible to reduce leakage currents to as low as 5 × 10^-14A/µm at VD= 10 V, more than two orders of magnitude lower than that in conventional-structure poly-Si TFT's. Optimization of the dopant concentration in offset-gate regions minimizes degradation of drive current, enabling high switching ratios exceeding 10⁸. Calculations based on the quasi-two-dimensional model indicate that the reduction in leakage current is due to a decrease in lateral electric field strength in the drain depletion region.     

Polycrystalline silicon thin-film transistors on a novel 800°C glass substrate

A new polycrystalline silicon thin-film transistor (TFT) technology using a potentially low-cost glass substrate is reported. Transistors are made using modified conventional n-channel MOS processes at temperatures of 800°C or less, with a final hydrogen implantation step. These transistors show leakage currents of 2 × 10^-11A/µm of channel width, ON-to-OFF current ratios of 1 × 10⁴at Vds= 9.0 V, and good dc stability. This combination of polycrystalline silicon transistors on potentially low-cost glass substrates offers a new option in the choice of active device technology for large-area flat-panel liquid crystal displays (LCD's).     

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration Noffin offset-gate regions. Leakage current markedly decreases from 1 × 10^-9to 2 × 10^-11A at VD= 10 V as Noffis varied from 1 × 10¹⁸to 1 × 10¹⁷cm^-3. A maximum ON/OFF current ratio of 10⁸is obtained at 1 × 10¹⁷cm^-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.     

Growth of high-purity semi-insulating bulk GaAs for integrated-circuit applications

Growth of high-purity bulk semi-insulating GaAs by the Liquid-Encapsulated Czochralski (LEC) method has produced thermally stable, high-resistivity crystals suitable for use in direct ion implantation. Large round substrates have become available for integrated-circuit processing. The implanted wafers have excellent electrical uniformity (±4 percent Vp) and have shown electron mobility as high as 4800cm²/V.s for Se implants with 1.7 × 10¹⁷cm^-3peak doping. Careful control of background doping through in situ synthesis has produced GaAs with Si concentrations as low as 6 × 10¹⁴cm^-3grown from SiO2crucibles. Detailed results of qualification tests for ion implantation in LEC GaAs will be discussed. Feasibility of successful high-speed GaAs large-scale integrated circuits using LEC substrates will be described.     

高斜率效率隧道结叠层激光器的研制

隧道结叠层激光器技术具有广泛的应用空间,如高斜率效率、高功率密度、多波长激光器等。采用LP-MOCVD系统生长隧道结材料,CCl4作为p型掺杂源,SiH4作为n型掺杂源,并采用δ掺杂技术,使得n+-GaAs的掺杂浓度大于1×1019/cm3,隧道结的面电阻率小于2×10-4Ω.cm2。设计生长了双叠层、三叠层材料,该材料制作的900nm双叠层激光器在200ns脉宽、20A工作电流下输出功率35W,斜率效率1.8W/A,是单层材料的1.8倍,隧穿结引入的压降约为0.15V;860nm三叠层激光器的斜率效率大于2.7W/A,是单层材料的2.7倍。     

The influence of Ge-implantation on the electrical characteristicsof the ultra-shallow junction formed by using silicide as a diffusionsource

The electrical characteristics of ultra-shallow p⁺/n junctions formed by implanting a 60 keV Ge⁺ into a TiSi₂ layer have been studied. A very low reverse leakage current density (≅0.4 nA/cm² at -5 V) and a very good forward ideality factor n (≅1.001) were achieved in these ultra-shallow p ⁺/n junctions. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth was measured to be 600 Å and the surface concentration was about 3 times higher than that of the conventional samples     

Optimization of oxygen-implanted silicon substrates for CMOS devices by electrical characterization

The use of oxygen-implanted silicon substrates for CMOS SOI device technology has great potential for use in VLSI and radiation-hardened circuits. The electrical characterization of such substrates is described by reference to CMOS devices fabricated directly into them; no epitaxial silicon was grown. Electrical parameters were related to the oxygen-implantation conditions of dose and temperature. Thermally generated oxygen donors in the top silicon layer were identified as being responsible for threshold voltage shifts and resistivity changes that altered transistor characteristics. Suitable boron implants enabled electrical parameter control to be maintained. Full island-to-substrate electrical isolation was only achieved for oxygen doses greater than 1.6 × 10¹⁸cm^-2, a larger dose from that required to create stoichiometric SiO2. Channel mobilities and NMOS back-channel leakage currents were found to be dependent on oxygen implant temperature; as a result a favorable implant window of 460-510 °C was established to fabricate ring oscillators twice as fast as bulk silicon counterparts for the same power dissipation.     

Study of bulk and elementary screw dislocation assisted reversebreakdown in low-voltage (<250 V) 4H-SiC p+-n junctiondiodes. I. DC properties

Given the high-density (~10⁴ cm^-2) of elementary screw dislocations (Burgers vector=1c with no hollow core) in commercial SiC wafers and epilayers, all large current (>1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the dc-measured reverse-breakdown characteristics of low-voltage (<250 V) small-area (<5×10^-4 cm² ) 4H-SiC p⁺-n diodes with and without elementary screw dislocations. Diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown current-voltage (I-V) knees, and highly localized microplasmic breakdown current filaments compared to screw dislocation-free devices. The observed localized 4H-SiC breakdown parallels microplasmic breakdown observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased     

The reverse anneal of junction characteristics in forming shallow p+-n junction by BF2+ implantation intothin Co films on Si substrate

Silicided shallow p⁺-n junctions, formed by BF₂ ⁺ implantation into thin Co films on Si substrates and subsequently annealed, showed a reverse anneal of junction characteristics in the temperature range between 550 and 600°C. The reverse anneal means behavior showing degradation of the considered parameters with increasing annealing temperature. A higher implant dosage caused a more distinct reverse anneal. The reverse anneal of electrical characteristics was associated with the reverse anneal of substitutional boron. A shallow p⁺-n junction with a leakage current density lower than 3 nA/cm₂, a forward ideality factor of better than 1.01, and a junction depth of about 0.1 μm was achieved by just a 550°C anneal     

On the behaviour of buried oxygen implanted layers in highly doped GaAs

Highly doped GaAs substrate material (doping level 10¹⁸ cm⁻³) has been implanted with 350 keV O⁺ ions with doses of 10¹⁴ – 10¹⁶ cm⁻² to produce high resistivity layers which are stable at high temperatures. LPE growth of flat GaAs epilayers onto the implanted wafers was achieved up to doses of about 1 × 10¹⁵ O⁺/cm² and 5 × 10¹⁵O⁺/cm² for RT and 200°C implants, respectively. N-o-n and p-o-n structures (o: oxygen implanted) were fabricated in which breakdown voltages of up to 15 V were obtained. Examples for application of this isolation technique are shown.     

Electrical characterization of crystal defects and oxygen in czochralski silicon using a gate-controlled diode

Defect generation in Czochralski (CZ) silicon crystal during heat treatment and effect of the defects on generation currents, measured by gate controlled diodes, were investigated. Sample wafers were obtained from an as-grown CZ silicon ingot which has a wide range of oxygen concentration but keeps other characteristics nearly constant. In the diode fabrication process, a two-step heat treatment method was utilized to control defect generation. It was found that stacking faults and dislocation loops, whose densities depend on oxygen concentration, increase the reverse current of the diode and the reverse current increases caused by defects vary with heat treatment condition. The most noticeable result was that the reverse current is enhanced by increasing oxygen concentration, even if no defect is observed in the device active region because of low defect density induced by heat treatment or of denuded zone formation. This result suggests the existence of some kind of electrically active defect caused by oxygen atoms in the crystal. Surface generation current is independent of crystal quality and two-step heat treatment conditions.     

Measurement of electron attachment processes in a high-temperature plasma

An experimental technique has been developed for measuring rate constants of electron attaching reactions as well as ion-molecule reactions in plasma at 2000-3000°K. Reaction product ions are mass analyzed and rate constants are obtained from plots of the collected ion current. The rate constant for O^-formation from N2O varies from about 3 to 9×10^-9cm³/s over the temperature range of 2400-3000°K while the rate constant for F^-formation from SF6varies from 2.8 to 4×10^-10cm³/s for temperatures from 2775 to 3000°K. A brief survey of experimental techniques for measuring electron attachment rate constants at lower temperatures is also given, together with a comparison of these rate constants and present high-temperature values.     

Formation of thermal donors in SIMOX material

Thermal oxygen donor generation in SIMOX material formed in Czochralski (CZ) and oxygen free float zone (FZ) silicon was investigated by Hall and photoluminescence techniques. It was determined that residual interstitial oxygen was introduced to silicon by the SIMOX buried oxide formation process thus increasing the possibility of thermal donor creation. Significantly, thermal donor generation was identified and localized to the top silicon region in FZ material. The detected concentration of residual oxygen was on the order of 5 × 10¹³ cm^-3 and is negligible when compared to the intrinsic oxygen concentration of the starting CZ bulk material.     

Anomalous effects of lamp annealing in modulation-doped In0.53Ga0.47As/In0.52Al0.48As and Si-implanted In0.53Ga0.47As

The effects of pulsed halogen-lamp annealing on modulation-doped In0.53Ga0.47As/In0.52Al0.48As heterostructures and Si-implanted In0.53Ga0.47As have been studied to determine the suitabiiity of this process in the fabrication of high-performance field-effect transistors. Implantation and annealing of these materials are necessary for contact and self-aligned gate formation. Mobilities as high as 7400 cm²/ V . s are measured at 300 K in undoped molecular-beam epitaxy In-GaAs implanted with 8 × 10¹²cm^{-2 29}Si⁺and lamp annealed at 700°C for 5 s. Anomalous overactivations (up to 120 percent) are observed in these layers When silox encapsulation is used during annealing, but the effect is absent for GaAs proximity capping. Sharp decreases in sheet-electron concentration and mobility occur in the normal modulation-doped structures for annealing temperatures > 750°C, while this trend is much smaller in the inverted structures. Arsenic loss from the In-AlAs doping layer is attributed as the main mechanism for this behavior, which makes the inverted structure more suitable for device processing. Depth profiling in the modulation-doped structures indicates that there may be serious pinchoff problems in these devices when annealed at higher temperatures due to outdiffusion of impurities from the InP substrate. Values of interdiffusion coefficients at the InGaAs/ InAIAs heterointerfaces, being reported for the first time, are almost three orders higher than those measured in the GaAs/AIAs systems.     

Reduction in minority carrier storage effect by fluorine ion implantation damage

Damage is produced in p-n diodes by fluorine ion implantation to reduce minority carrier storage effect. The switching time, reverse leakage current, andI-Vcharacteristics were investigated for annealing temperature between 450°C and 650°C. The accelation energy is 130 keV and doses are 10¹³-10¹⁵/cm². Annealing causes restoration in switching time, but leakage current increases with annealing temperature rise for doses more than 1 × 10¹⁴/cm². The best diodes indicate 1.5-order reduction in switching time and 10 nA in reverse leakage current. These properties, caused by implantation damage, are retained after long-cycle annealing at 450°C and are expected to be stable under practical use. These diodes can be obtained by annealing at 450°C and they furnish satisfactory diode performance.     

Device characterization of p-channel AlGaAs/GaAs MIS-like heterostructure FET's

p-channel AlGaAs/GaAs MIS-like heterostructure FET's (p-MIS HFET's) are characterized concerning their gate-source leakage current. Device performance is confirmed to improve approximately inversely to layer thickness dtbetween the channel and metal gate, at low gate voltages. A high transconductance gmof 110 ms. mm-1is obtained at 77 K by reducing dtto 20 nm. Maximum transconductance is limited by gate-source leakage current Igs. Igsis governed mainly by the leakage current through the ion-implanted gate edge and is reduced by decreasing the dose level of ion-implantation at the gate edge to 2 × 10¹³cm^-2. The contact resistance is reduced to about 0.1 ω. mm by ion implantation into the ohmic contact region to a dose of 2 × 10¹⁴cm^-2. Calculations indicate that, by reducing Igsand the gate-source resistance to 1 ω. mm with the lightly doped drain (LDD) structure, gmaround 200 mS. mm^-1at 300 K and 300 mS. mm^-1at 77 k are achievable with a 1-µm gate structure.     

Defects in annealed 1.5 MeV boron implanted p-type silicon

Effects of temperature and dosage on the evolution of extended defects during annealing of MeV ion-implanted Czochralski (CZ) p-type (001) silicon have been studied using transmission electron microcopy. Excess interstitials generated in a 1 10¹⁵ cm⁻²/1.5 MeV B⁺ implanted Si have been found to transform into extended interstitial {311} defects upon rapid thermal annealing at 800°C for 15 sec. During prolonged furnace annealing at 960°C for 1 h, some of the {311} defects grow longer at the expense of the smaller ones, and the average width of the defects seems to decrease at the same time. Formation of stable dislocation loops appears to occur only above a certain threshold annealing temperature (∼1000°C). The leakage current in diodes fabricated on 1.5 MeV B⁺ implanted wafers was found to be higher for a dosage of 1 10¹⁴cm⁻² and less, as compared to those fabricated with a dosage of 5 10¹⁴ cm⁻² and more. The difference in the observed leakage current has been attributed to the presence of dislocations in the active device region of the wafers that were implanted with the lower dosage.