Combining Pilot-Symbol-Aided Techniques for Fading Estimation and Diversity Reception in Multipath Fading Channels

A novel pilot-symbol-aided (PSA) fading estimation technique that combines the estimates from a conventional PSA technique and a bandwidth-efficient PSA technique to achieve better performances is proposed for digital signals in multipath fading channels. The conventional technique has better performances at low signal-to-noise ratios (SNRs), while the bandwidth-efficient technique is superior at high SNRs. Monte Carlo computer simulation has been used to assess the effects of the proposed combining technique on the bit-error-rate (BER) performances of 16-ary quadrature-amplitude-modulation (16QAM), with and without two-branch diversity reception, in a flat Rayleigh fading channel. Results have shown that the combining technique has the advantages of both of the conventional technique and the bandwidth-efficient technique and is more preferred for use with diversity reception. Man-Hung Ng received a BSc degree in Computer Studies from City University of Hong Kong in 1991. He worked as a computer programmer in Hong Kong from 1991 to 1995. In 1996, he obtained a MSc degree in Communication and Radio Engineering from King's College London. He joined the University of Hong Kong as a research assistant in 1997, and completed a PhD degree in mobile communications in 2001. He joined Lucent Technologies N.S. UK in 2001 and is now a principal standards engineer. Sing-Wai Cheung received the BSc degree in Electrical and Electronic Engineering from Middlesex University, U.K. in 1982 and the PhD degree from Loughborough University of Technology, U.K. in 1986. From 1986–1988, he was a post-doctorate research assistant in the Communications Research Group of King's College, London University. During 1988–1990, he was with the Radio and Satellite Communications Division in British Telecom Research Laboratories (now British Telecom Laboratories). He joined the Department of Electrical and Electronic Engineering at the University of Hong Kong in 1990 and is now an Associate Professor. He contributes regularly courses on mobile and satellite communications systems. His current research interests include modulation, coding, fading compensation and diversity and MIMO for mobile and satellite communications systems.     

Biography - Seymour B. Cohn

Seymour B. Cohn (S'41-A'44-M'46-SM'51-F'59) was born in Stamford, Conn., on October 21, 1920. After receiving the B. E. degree in electrical engineering from Yale University, New Haven, Conn., in 1942, he worked for the Radio Research Laboratory of Harvard University, Cambridge, Mass., specializing in UHF and microwave receivers, circuits, and filters. In 1944 he represented the Radio Research Laboratory as a technical observer with the U. S. Air Force in the Mediterranean Theater of Operations. Following the disbanding of the Radio Research Laboratory at the end of 1945, he enrolled as a graduate student at Harvard University and was awarded the M.S. degree in communication engineering in 1946, and the Ph.D. degree in engineering science and applied physics in 1948.     

Systematic Synthesis of Active-RC Circuit Building-Blocks

In this paper, we show how some basic building blocks for active-RC circuit design, such as amplifiers, impedance converters and simulated inductance circuits, may be synthesised in a systematic way by expansion of their port admittance matrices. The circuit topology emerges from the synthesis procedure, allowing all possible implementations to be identified and explored. Nullors representing ideal op-amps and transistors are represented within the nodal admittance matrix of a synthesised circuit by linked infinity parameters. In nodal admittance matrices describing ideal circuits synthesised, the replacement of linked infinity parameters by finite parameters provides a seamless transition to non-ideal analysis and practical circuit design.Now with the Singaporean Armed Services.David Haigh was born in Middlesex, England, in 1946. He obtained the B.Sc. degree in Electrical Engineering from Bristol University in 1968 and in 1976 he received the Ph.D. degree from the University of London. From 1968 until 1972 he worked under Dr. Wolja Saraga first at the GEC Hirst Research Centre and then, from 1972, at Imperial College London where he worked on microelectronic high precision filters. In 1987 he joined the staff of the Electronic and Electrical Engineering Department of University College London, where he studied analogue integrated circuit design with particularly interest in high frequency circuits. In 2003 he re-joined the Department of Electrical and Electronic Engineering at Imperial College London, where his interests broadened to include general approaches for analogue circuit synthesis. He is editor-in-chief (Europe) of the Analog Integrated Circuits and Signal Processing Journal.Fang Qun Tan graduated with a B.Eng. degree from Imperial College London in 2002. He then studied for the M.Sc. in Analogue and Digital integrated Circuit Design at Imperial College and graduated with distinction in 2003. His M.Sc. project was on the subject of systematic synthesis methods for analogue circuits. At present Fang Qun is with the Singapore Armed Services.Christos Papavassiliou was born in Athens, Greece, in 1960. He received the B.Sc. degree in physics from the Massachusetts Institute of Technology and the Ph.D. degree in Applied Physics from Yale University. He has worked on monolithic microwave integrated circuit (MMIC) design and measurements at FORTH in Crete, Greece, and has been involved in several European and regional projects on GaAs MMIC technology. In 1996 he joined Imperial College London, where he is currently a Senior Lecturer. He currently works on SiGe technology development as well as instrumentation and substrate noise coupling in mixed mode integrated circuit design. He has 30 publications.     

Essential Considerations in Implementing the Smart Antenna System for Downlink Beamforming

This paper addresses some essential problems that have to be taken into consideration in implementing the smart antenna base station (SABS) for downlink beamforming. In order to provide proper downlink beamforming as well as uplink beamforming, a pragmatic procedure of automatic calibration is proposed. Through the experimental test, we confirm that the proposed calibration technique has eliminated the problem of the phase differences of the signal path associated with each antenna. Also, in this paper, we first analyze the multipath condition under which the auxiliary pilot becomes indispensable for detecting the data transmitted on the data channel and what happens if the auxiliary pilot is not available. Then, the performance of the downlink beamforming utilizing the auxiliary pilot is analyzed through the computer simulations. Finally, we present a comparison of downlink communications to uplink ones in terms of throughputs available at each of uplink and downlink communications. Weon-Cheol Lee received the B.S, M.S, and Ph.D. degree in Electronic Communication Engineering from Hanyang University, Korea, in 1992, 1994, 2005, respectively. From 1994 to 2000, he was with LG Electronic Inc., where he had worked for developing the digital VCR, digital cable modem, digital TV. Since 2001, he has been a professor with department of information and communications, Yong-in Songdam College, Korea. His research interests include smart antennas, mobile communications beyond the third generation, digital broadcasting technology, and communication signal processing. Dr. Lee also received the Best Research Paper Award and Excellent Research Engineer Award from LG Electronics, respectively. Seungwon Choireceived the BS degree from Hanyang University, Seoul, Korea, and the M.S. degree from Seoul National University, Korea, 1980 and 1982, respectively, both in electronics engineering, the MS degree (computer engineering) in 1985, and the PhD degree (electrical engineering), in 1988, both from Syracuse University, Syracuse, NY. From 1988 to 1989 he was with the Department of Electrical and Computer Engineering of Syracuse University, Syracuse, NY, as an Assistant Professor. In 1989 he joined the Electronics and Telecommunications Research Institute, Daejeon, Korea. From 1990 to 1992 he was with the Communications Research Laboratory, Tokyo, Japan, as a Science and Technology Agency fellow, developing the adaptive antenna array systems and adaptive equalizing filters. He joined Hanyang University, Seoul, Korea, in 1992 as an assistant professor. He is a professor in the School of Electrical and Computer Engineering of Hanyang University. Since 2003, Dr. Choi has been serving as a Vice Chairman and the representative of the ITU region 3 for SDR (Software Defined Radio) Forum and as a Director of the HY-SDR Research Center, MIC, Korea. His research interests include digital communications and adaptive signal processing with a recent focus on the implementation of the smart antenna systems for both mobile communication systems and wireless data systems. Jae-Moung Kim received the BS degree from Hanyang University, Korea in 1974, the MSEE degree from University of Southern California, USA in 1981, and the PhD degree from Yonsei University, Korea in 1987. He was a Vice President of Radio {&} Broadcasting Technology Laboratory and Director of Satellite Communication System Department at Electronics and Telecommunications Research Institute (ETRI) from September 1982 to March 2003. Since April of 2003, he has been a Professor in the Graduate School of Information Technology and Telecommunications, Inha University. He is a board member of directors of Korean Institute of Communication Science (KICS), a Vice President of Korea Society of Broadcast Engineers (KOSBE) and a senior member of IEEE. His research background is telecommunication systems modeling and performance analysis of broadband wireless access systems, mobile communications, satellite communications and broadcasting transmission technologies.     

Traffic Models and Blocking Probabilities for Two-Fold and Three-Fold SDMA Communication Systems

Spectrum efficiency is a constant challenge in the design of wireless networks. Space-division-multiple-access (SDMA) is a promising approach to achieve higher spectral efficiency which reuses bandwidth via multiplexing signals based on their spatial signature. Several different studies have shown that SDMA can effectively improve system capacity in a mobile environment. In this paper, we present a new Markov chain traffic model for a duplicate-at-last (DL) approach [IEE Proceedings on Communication 146 (1999) 303] in two-fold and three-fold SDMA systems. Simplified blocking probability formulations for two-fold and three-fold SDMA are also derived. Simulations based on a common method of spatial separation check for channel allocation in SDMA are presented to evaluate the probability of successfully creating two-fold and three-fold SDMA channels. The simulation, as well as analytical, results indicate that the SDMA system can reduce the blocking probability of the calls and result in more traffic loading than a traditional cellular system. The results also show that our simplified approaches not only can reduce the computational complexity, but can also accurate approximate two-fold and three-fold SDMA performance. Wen-Jye Huang received the B.S. degree in electrical engineering from Tatung Institute of Technology, Taipei, Taiwan, in 1991, the M.S. degree in electrical engineering from Ohio University, Athens, OH, in 1997, and the Ph.D. degree in electrical engineering from The Pennsylvania State University, University Park, PA, in 2001. Since 2002, he joined the Department of Electrical Engineering, Chang Gung University, Kwei-San, Tao-Yuan, Taiwan, as an assistant professor. His research activities include smart antenna, SDMA, and MC-CDMA techniques. John F. Doherty received the B.S. degree (with honors) in engineering science from the College of Staten Island, City University of New York, in 1982, the M.Eng. degree in electrical engineering from Stevens Institute of Technology, Hoboken, NJ, in 1985, and the Ph.D. degree in electrical engineering from Rutgers University, New Brunswick, NJ, in 1990. He was an integrated circuit reliability engineer with IBM, from 1982 to 1984. From 1985 to 1988, he was member of the technical staff at AT&T Bell Laboratories, working in sonar signal processing. In 1990, he joined the Electrical and Computer Engineering Department, Iowa State University, Ames, as an assistant professor and Harpole Entair fellow. He is currently an associate professor of electrical engineering with The Pennsylvania State University, University Park. His current research activities include interference rejection in wireless communication systems, spatial-division multiple-access techniques, and radar target detection techniques. He is a former AFOSR summer faculty research fellow at the Rome Laboratory, Rome, NY, and an Army Research Office Young Investigator.     

A Novel Calibration Method for Phase-Locked Loops

A novel method to calibrate the frequency response of a Phase-Locked Loop is presented. The method requires just an additional digital counter to measure the natural frequency of the PLL; moreover it is capable of estimating the static phase offset. The measured value can be used to tune the PLL response to the desired value. The method is demonstrated mathematically on a typical PLL topology and it is extended to fractional-N PLLs. A set of simulations performed with two different simulators is used to verify the applicability of the method.This work was carried out as a part of an internship at the QCT department of Qualcomm CDMA Technologies.Marco Cassia was born in Bergamo, Italy, 1974. He received the M.Sc. degree in engineering from the Technical University of Denmark, Lyngby, Denmark, in May 2000 and the M.Sc. degree in electrical engineering from Politecnico di Milano, Italy, in July 2000.From July 2001 to July 2002 he was with the QCT department of Qualcomm CDMA Technologies, San Diego, working in the field of direct modulation synthesizers. He is currently working toward the Ph.D.degree at the Technical University of Denmark.His main research interests are in the areas of low-power low-voltage RF systems.Peter Shah was born in Copenhagen Denmark in 1966. He completed his MScEE and Ph.D at The Technical University of Denmark in 1990 and 1993 respectively. From 1993 to 1995 he was a post doctoral research assistant at Imperial College in London, England, working on switched-current circuits. In 1996 he joined PCSI in San Diego (subsequently acquired by Conexant) as an RFIC design engineer, working on transceiver chips for the PHS cellular phone system. In 1998 he joined Qualcomm, also in San Diego, where he worked on RFICs for CDMA mobile phones and for GPS. In December 2002 he joined RFMagic where he is currently working on RFICs for consumer electronics. His research interests lie mainly in RFIC architecture and design, including sigma-delta PLLs and A/D and D/A converters, LNAs, mixers, and continuous-time filters.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, I²L devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ØrstedDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

A Reconfigurable Gaussian/Triangular Basis Functions Computation Circuit

A CMOS Gaussian/Triangular Basis functions computation circuit suitable for analog neural networks is proposed. The circuit can be configured to realize any of the two functions. The circuit can approximate these functions with relative root-mean-square error less than 1%. It is shown that the center, width, and peak amplitude of the dc transfer characteristic can be independently controlled. SPICE simulation results using 0.18 μ m CMOS process model parameters of TSMC18 technology are included. Muhammad Taher Abuelma'Atti was born in Cairo, Egypt, in 1942. He received the B.Sc. degree in Electrical Engineering in 1963 from the University of Cairo, Cairo, Egypt, the Ph.D. degree in 1979 and the Doctor of Science degree in 1999 both from the University of Bradford, Bradford, England. From 1963 to 1967, he worked at the Military Technical College in Cairo as a Teaching Assistant. He was with the Iron and Steel Company in Helwan, Cairo, from 1967 to 1973 as a Senior Electrical Engineer. From 1973 to 1976 he was with the College of Engineering, University of Riyadh, Saudi Arabia, as a Teaching Assistant. From 1980 to 1981, he worked with the Faculty of Engineering, University of Khartoum, Sudan, as an Assistant Professor, and from 1981 to 1982 he was with the College of Engineering, King Saud University, Riyadh, Saudi Arabia, as an Assistant Professor. In 1982 he joined the College of Engineering, University of Bahrain and in 1987 he became an Associate Professor. In 1991 he joined the College of Engineering Sciences, King Fahd University of Petroleum and Minerals, Dhahran, Saudi Arabia, where he became a Full Professor in January 1995. Dr. Abuelma'Atti is the recipient of the 1994/1995 Excellence in Teaching Award and the 1995/1996 and 2000/2001 Excellence in Research Award. Both at King Fahd University of Petroleum and Minerals. Dr. Abuelma'Atti is a contributor to Encyclopedia of RF and Microwave Engineering, Kai Chang, Editor, (New York: John Wiley, 2005), Survey of Instrumentation and Measurement, S.A. Dyer, Editor, (New York: John Wiley, 2001), The Encyclopedia of Electrical and Electronic Engineering, J.G. Webster, Editor, (New York:John Wiley, 1999), and Selected Papers on Analog Fiber-Optic Links, E.I. Ackerman, C.H. Cox III and N.A. Riza, Editors, SPIE Milestone Series, (Washington: SPIE Optical Engineering Press, 1998). His research interests include problems related to analysis and design of nonlinear electronic circuits and systems, analog integrated circuits and active networks design. He is the author or co-author of over 500 journal articles and technical presentations. Abdullah Bakri Shwehneh was born in Aleppo Syria, in 1973. He received the B. Sc. degree in electrical engineering in 1998 from Sumy State University, Sumy, Ukraine. In 2001, he received the Postgraduate Diploma in Automatic Control from Aleppo State University, Aleppo, Syria. In 2001, he joined the “Electronic Brain Company for Computer and Electronics” as an Electronic & Computer Engineer and since 2002, he is with King Fahd University of Petroleum and Minerals (KFUPM), Dhahran, Saudi Arabia, as a Research Assistant. In June 2005 he obtained his Master of Science Degree in Analog Electronics from KFUPM. At present he is a Ph.D. student at KFUPM. His main interests are in Nonlinear circuits, VLSI Analog Design and Neural Networks hardware implementation.     

Electrical Engineering Hall of Fame: John A. Fleming

In 1933, the Institute of Radio Engineers (IRE) selected John A. Fleming as the recipient of its Medal of Honor. He was cited "for the conspicuous part he played in introducing physical and engineering principles into the radio art." Earlier, he had received the Hughes Medal of the Royal Society of London, in 1910, and the Faraday Medal of the British Institution of Electrical Engineers (IEE), in 1928. During his long career, he authored more than 100 technical papers and several influential textbooks. He is remembered as the inventor of the "Fleming valve," an thermionic diode which was a precursor of vacuum-tube amplifiers     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

A New Differential CMOS Current-Mode Preamplifier for GBps Data Communications

This paper presents a new low-voltage fully differential CMOS current-mode preamplifier for GBps data communications. The number of transistors between the power and ground rails is only two so that the minimum supply voltage is one threshold voltage plus one pinch-off voltage. The preamplifier is a balanced two-stage configuration such that the effect of bias-dependent mismatches is minimized. A new inductive series-peaking technique is introduced to increase the bandwidth by utilizing the resonance characteristics of LC networks. In addition, a new negative differential current feedback technique is proposed to boost the bandwidth and to reduce the value of peaking inductors. The preamplifier has been implemented in TSMC 0.18 μm, 1.8 V, 6-metal mixed-mode CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3 pF photodiode capacitance, simulation results demonstrate that the preamplifier has bandwidth of 3.5 GHz and provides a transimpedance gain of 66 dBΩ. The total chip area is approximately 1 mm² and the DC power consumption is about 85 mW. Bendong Sun received the B.Eng. degree in electrical engineering from Shanghai Jiaotong University, Shanghai, China, in1992, and the MASc degree in electrical and computer engineering from Ryerson University, Toronto, Ontario, Canada, in 2003. He is currently working towards the Ph.D. degree in electrical and computer engineering at University of Waterloo, Waterloo, Ontario, Canada. During 1992 through 1998 he was a Design Engineer at China Electronics Engineering Design Institute, Beijing, China. From 1998 to 2000 he worked for Bently Nevada Corporation, a GE Power Systems business, as a System Engineer. Since 2001, he has been a Research Assistant with the System-on-Chip Laboratory at Ryerson University. His research interests include design of analog and mixed-signal integrated circuits for high-speed data communications. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc degree in chemical engineering and PhD degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching" award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Ajoy Opal (S'86-M'88) received the B. Tech degree from Indian Institute of Technology, New Delhi, India in 1981, and the MASc and PhD degrees from University of Waterloo, Waterloo, Ontario, Canada in 1984 and 1987, respectively. During 1989–92 he worked for Bell-Northern Research in the area of analog circuit simulation. He joined the Department of Electrical and Computer Engineering, University of Waterloo in 1992 and currently a Full Professor. Dr. Opal works in the area of simulation of analog and mixed digital-analog circuits, such as, switched capacitor, switched current, oversampled sigma-delta modulators. Other interests include circuit theory and filter design.     

A Broadband Double-Conversion RF Tuner

A prototype design of upconverter and downconverter units for a double-conversion cable-modem RF tuner are presented. The upconverter upconverts a channel from 47–862 MHz input band to around 1575 MHz intermediate frequency. The image-reject downconverter shifts the channel to 36.125 MHz (EU) or to 43.75 MHz (US). The upconverter includes a variable-gain low-noise amplifier, a double-balanced mixer, a three-stage VCO bank for LO generation and a divide-by-two circuit for driving an external PLL. The downconverter includes a LNA, image-reject mixers in Hartley configuration, a 3-stage polyphase filter, an IF-amplifier and a SAW driver. For the second LO generation the circuit includes a 6-GHz on-chip VCO, a divide-by-four circuit for quadrature LO and a divide-by-16 for feeding an external PLL. Signal reversal switching in the LO buffer can be used for the selection of LSB/USB injection. All building blocks are presented in this paper and experimental results are given from the upconverter, downconverter, and RF tuner demonstrator including SAW filters with center frequencies at 1575 and 44 MHz. The circuits are fabricated in a 0.9- m SiGe bipolar process.Kari Stadius received the M.Sc. degree in electrical engineering in 1994 and the Licentiate of Technology degree in 1997, both from Helsinki University of Technology, where he is currently working as a research scientist. His research interests include the design and analysis of RF transceiver blocks with special emphasis on RF oscillators and modelling of passive components.Arto Malinen was born in Savonlinna, Finland, in 1978. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT), Finland, in 2003, where he is currently working towards the Ph.D. degree. He is a research engineer with the Electronic Circuit Design Laboratory, HUT. His main research interests are in RF IC design, including low-noise amplifiers and mixers.Petri S. Järviö was born in Kitee on December 10, 1975. He received the M.Sc (EE) degree in 2001 from the Helsinki University of Technology. From 1999 to 2001 he worked as a research assistant at the Electronic Circuit Design Laboratory in Helsinki University of Technology. Nowadays he works at Finnish Defence Forces Technical Research Centre, Electronics and Information Technology Division where his research area is Radio frequency sensors.Kari A.I. Halonen was born in Helsinki, Finland, in 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987. From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Centre of Finland. From 1984 to 1987 he was research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Centre (1990–1993). He was on leave of absence the academic year 1992/93, acting as R{&}D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of the Electrical Engineering and Telecommunications, Helsinki University of Technology. He specializes in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. He is author or co-author of a hundred international and national conference and journal publications on analog integrated circuits.     

Opamp gain insensitive MASH sigma delta modulator for wide bandwidth applications

This work presents a means to enhance the immunity of non-ideal opamp gain effect of the fourth order multi-stage noise shaped (MASH) sigma-delta modulator (SDM) for wide bandwidth applications. The first stage of the SDM is a low-distortion single-loop second order SDM, while the second stage is a low-distortion interpolative second order SDM with Chebyshev type II filter technique. Theoretically, the conventional MASH SDM is impacted by the nonlinear finite gain of the operational amplifier. This impact may have two main phenomena. First, it leaks the incompletely corrected quantization error to the output. Secondly, the nonlinearity causes the harmonic distortion of the input signal. The proposed architecture can reduce the distortion and the sensitivity of the nonlinear finite opamp gain to improve the performance by using low-distortion technique in the MASH SDM. Furthermore, the lower power budget and simplified digital cancellation logic can be achieved. The experimental results indicate that the dynamic range (DR) can reach 87dB with power dissipation of 65 mW. A test SDM chip for Asymmetric Digital Subscriber Line (ADSL) application is designed and implemented by TSMC 0.25 um 1P5M process. Jen-Shiun Chiang was born in Taichung Taiwan, ROC in 1960. He received the B.S. degree in electronics engineering from Tamkang University, Taipei, Taiwan in 1983. In 1988, he received the M.S. degree in electrical engineering from University of Idaho, Moscow Idaho, USA. In 1992, he received the Ph.D. degree in the electrical engineering from Texas A & M University, College Station Texas, USA. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992. Currently, he is a Professor and Department Chair of the Department of Electrical Engineering at Tamkang University. Dr. Chaings research interest includes computer arithmetic, computer architecture, digital signal processing for VLSI architecture, architecture for image data compressing, analog to digital data conversion, and low power circuit design. Hsin-Liang Chen was born in Taipei, Taiwan, in 1974. He received the B.S. degree and M.S. degree in the electrical engineering from Tamkang University, Taipei, Taiwan, in 1997 and 2003, respectively. He is currently working toward the Ph.D. degree at Tamkang University. His research interest focuses on mixed-signal CMOS circuit, sigma delta ADC, and low power circuit.     

A New Low Latency Parallel FIR Filter Scheme

A new array type parallel scheme for an FIR digital filter is presented in this paper. The proposed scheme is based on the structure of the carry-save array multiplier where each cell implements the computation of an FIR filter at the bit-level. This structure leads to latency independent of the number of the filter taps. The proposed scheme is pipelined at the bit-level, is systolic at the cell-level and requires less hardware than other schemes based on discrete multipliers.Paraskevas Kalivas received his Diploma and Ph.D. degree in electrical and computer engineering from the National Technical University of Athens, Greece, in 1990 and 2000 respectively.His research interests include computer arithmetic and efficient realization of arithmetic circuits and digital filters.Vassilis Vassilakis received his Diploma in electrical and computer engineering from NationalTechnical University of Athens, Greece, in 1997. He isworking toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include efficient circuit implemenation of DSP algorithms and java processor architectures.Chris Meletis received his Diploma in electrical and computer engineering from National Technical University of Athens in 1997. Currently, he is working toward the Ph.D. degree in electrical engineering at National Technical University of Athens.His research interests include multirate filter banks, digital filter design and their efficient realization.Kiamal Z. Pekmestzi received his Diploma in electrical engineering from the National Technical University of Athens, Greece, in 1975. From 1975 to 1981, he was a research fellow in the Electronics Department of the Nuclear Research Center Demokritos. He received his Ph.D. in electrical engineering from the University of Patras, Greece, in 1981.From 1983 to 1985, he was a professor at the Higher School of Electronics in Athens. Since 1985, he has been with the National Technical University of Athens, where he is currently a professor. His research interests include computer arithmetic, VLSI digital filters and VLSI design automation.     

The Impact of Delay Spread on Irreducible Errors for Wideband Channels on Industrial Sites

To allow development of highly reliable wide-band mobile communications on industrial sites it is imperative to be able to characterise the multi-path performance of the propagation. This performance can be statistically characterised with channel impulse response (CIR) results. Such results from a wide variety of industrial environments are used with bit error ratio (BER) measurements to predict irreducible-BER performance as a function of RMS delay spread (RDS). These are compared to Chuang's simulation results and are first experimental results to challenge and to some extent confirm those results. The way these results can be used in developing communications systems for industrial sites is discussed. The work described in this paper took place at the University of Leeds, U.K. and was supported by the EC under ESPRIT project 27035, ‘mofdi’. Andrew H. Kemp received a BSc from the University of York, UK, in 1984 and Ph.D. from the University of Hull, U.K., in 1991. His doctoral studies investigated the use of complementary sequences in multi-functional architectures for use in CDMA systems. He spent several years working in Libya and South Africa assisting in seismic exploration and worked at the University of Bradford as a research assistant investigating the use of Blum, Blum and Shub sequences for cryptographically secure 3rd generation systems. More recently he helped develop wireless fieldbus systems for industrial sites and is now lecturing at the University of Leeds, U.K. in communications. Andrew has over 30 scientific journal and conference papers and a book chapter published. His research interests are in multi-path propagation studies to assist system development and wireless broadband connection to computer networks incorporating quality of service provision. Stephen K. Barton received the BSc(Eng) degree in Electronic and Electrical Engineering from University College London, U.K., in 1970 and the MSc degree in Telecommunications Systems from the University of Essex, U.K., in 1974. From 1970 to 1976 he was employed by Marconi Research Laboratories, principally on high speed fast acquisition modems for satellite TDMA. From 1976 to 1980 he was with Her Majesty's Government Communications Centre, working on GaAs FET oscillators and conformal antennas. From 1980 to 1985, he was with the Rutherford Appleton Laboratory, where he originated the Communications Engineering Research Satellite project. From 1985 to 1989 he was with Signal Processors Ltd. working on Adaptive TDMA modems and digital receivers generally. From 1989 to 1998 he was with the University of Bradford, from 1998 to 1999 he was with the University of Leeds, and since 1999 he is with the University of Manchester. His research interests include Wireless LANs, MAC and routing protocols, multi-carrier modulation/demodulation, CDMA, channel equalisation and near/far resistant detection algorithms. From 1993 to 1996 he was chairman of Working Group 3: Broadband Systems, of the European Co-operation in Science and Technology programme: COST 231: Evolution of Land Mobile Radio (including personal) Communications. From 1997 to 2000 he was chairman of Working Group 1: Radio System Aspects, of COST 259: Wireless Flexible Personalised Communications. Since 2001, he is the UK National representative to COST 273: Towards Mobile Broadband Mutimedia Networks. Prof Barton is a Fellow of the IEE and a Senior Member of the IEEE.     

Digital PWM controller with one-bit noise-shaping interface

Conventionally, pulse width modulation (PWM) controllers for DC-DC switching power converters have been implemented in pure analog circuits. However, recent research showed the possibility of digital controllers with several advantages such as robustness, fast design time, and high flexibility. Since DC-DC converted output voltage is analog in nature, an analog-to-digital interface circuit is always essential even in digital PWM controllers. A simple and efficient delta-sigma modulator is used as a conversion circuit in our silicon implementation. Measurement results show good voltage regulations. Jeongjin Roh received the B.S degree in electrical engineering from the Hanyang University, Korea, in 1990, the M.S. degree in electrical engineering from the Pennsylvania State University in 1998, and the Ph.D. degree in computer engineering from the University of Texas at Austin in 2001. From 1990 to 1996, he worked at Samsung Electronics in Kiheung, Korea, as a senior circuit designer for several mixed-signal products. From 2000 to 2001, he worked at Intel Corporation in Austin, Texas, as a senior analog designer for wireless communication circuits. In 2001, he joined the faculty at the Hanyang University in Ansan, Korea. His research interests include low-power analog circuits, power management ICs, and oversampled delta-sigma converters.     

Dynamic utility and price based radio resource management for rate adaptive traffic

This paper explores analytical Radio Resource Management models where the relationship between users and services is mapped through utility functions. Compared to other applications of these models to networking, we focus in particular on specific aspects of multimedia systems with adaptive traffic, and propose a novel framework for describing and investigating dynamic allocation of resources in wireless networks. In doing so, we also consider economic aspects, such as the financial needs of the provider and the users’ reaction to prices. As an example of how our analytical tool can be used, in this paper we compare different classes of RRM strategies, e.g., Best Effort vs. Guaranteed Performance, for which we explore the relationships between Radio Resource Allocation, pricing, provider’s revenue, network capacity and users’ satisfaction. Finally, we present a discussion about Economic Admission Control, which can be applied in Best Effort scenarios to further improve the performance. Part of this work has been presented at the conference ACM/IEEE MSWiM 2004, Venice (Italy). Leonardo Badia received a Laurea degree (with honors) in electrical engineering and a Ph.D. in information engineering from the University of Ferrara, Italy, in 2000 and 2004, respectively. He was a Research Fellow at the University of Ferrara from 2001 to 2006. During these years, he also had collaborations with the University of Padova, Italy, and Wireless@KTH, Royal Institute of Technology, Stockholm, Sweden. In 2006, he joined the “Institutions Markets Technologies” (IMT) Institute for Advanced Studies, Lucca, Italy, where he is currently a Research Fellow. His research interests include wireless ad hoc and mesh networks, analysis of transmission protocols, optimization tools and economic models applied to radio resource management. Michele Zorzi received a Laurea degree and a Ph.D. in electrical engineering from the University of Padova in 1990 and 1994, respectively. During academic year 1992–1993, he was on leave at UCSD, attending graduate courses and doing research on multiple access in mobile radio networks. In 1993 he joined the faculty of the Dipartimento di Elettronica e Informazione, Politecnico di Milano, Italy. After spending three years with the Center for Wireless Communications at UCSD, in 1998 he joined the School of Engineering of the University of Ferrara, Italy, where he became a professor in 2000. Since November 2003 he has been on the faculty at the Information Engineering Department of the University of Padova. His present research interests include performance evaluation in mobile communications systems, random access in mobile radio networks, ad hoc and sensor networks, energy constrained communications protocols, and broadband wireless access. He was Editor-In-Chief of IEEE Wireless Communications, 2003–2005, and currently serves on the Editorial Boards of IEEE Transactions on Communications, IEEE Transactions on Wireless Communications, Wiley’s Journal of Wireless Communications and Mobile Computing, and ACM/URSI/Kluwer Journal of Wireless Networks, and on the Steering Committee of the IEEE Transactions on Mobile Computing. He has also been a Guest Editor of special issues in IEEE Personal Communications (Energy Management in Personal Communications Systems) and IEEE Journal on Selected Areas in Communications (Multimedia Network Radios).     

Domino Free 4-Path Time-Interleaved Second Order Sigma-Delta Modulator

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.Kye-Shin Lee received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 1992 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas.He was with LG Semicon Co. (now Hynix Semicon Inc.), Seoul, Korea from 1994 to 1999, where he was involved in mixed signal circuit design and testing of BW/Color CCD chipsets including timing/sync. signal generator, camera signal processor, USB camera interface, and sigma-delta CODECs for audio and voice band applications. His research has been focused on switched-capacitor circuits, sigma-delta modulators, and pipeline ADCs.Yunyoung Choi received the B.S. degree from Kwangwoon University, Seoul, Korea, in 1999 and the M.S. degree in electrical engineering from Texas A&M University, College Station, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the University of Texas at Dallas. He worked for Texas Instruments, Dallas, from May to December 2003 at the Wireless Business Unit. His research interest includes sigma-delta A/D and D/A converters for audio systems and RF applications.Franco Maloberti received the Laurea Degree in physics (summa cum laude) from the University of Parma, Parma, Italy, in 1968 and the Dr. Honoris Causa degree in electronics from the Instituto Nacional de Astrofisica, Optica y Electronica (Inaoe), Puebla, Mexico, in 1996.In 1993, he was a Visiting Professor at ETH-PEL, Zurich, Switzerland. He was Professor of Microelectronics and Head of the Micro Integrated Systems Group, University of Pavia, Pavia, Italy, and the TI/J.Kilby Analog Engineering Chair Professor at Texas A&M University, College Station. He is currently with the University of Pavia and an adjunct Professor at the University of Texas at Dallas. His professional expertise is in the design, analysis, and characterization of integrated circuits and analog digital applications, mainly in the area of switched-capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analog and mixed A/D design. He has written more than 250 published papers, three books, and holds 15 patents.Dr. Maloberti was a 1992 recipient of the XII Pedriali Prize for his technical and scientific contributions to national industrial production. He was co-recipient of the 1996 Institution of Electrical Engineers (U.K.) Fleming Premium for the paper “CMOS triode transistor transconductance for high-frequency continuous time filters.” He has been responsible at both technical and management levels for many research programs including ten ESPRIT projects and has served the European Commission as ESPRIT Projects’ Evaluator and Reviewer and as a European Union expert in many Initiatives. He served the Academy of Finland on the assessment of electronic research in Academic institutions and on the research programs’ evaluator. He was Vice-President, Region 8, of the Editor of IEEE Circuits and Systems (CAS) Society from 1995 to 1997 and an Associate Editor of the IEEE Transcations on Circuits and Systems II. He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millennium Medal. He is the President of IEEE Sensors Council and a member of the Board of Governors of the IEEE CAS Society. He is also the member of the Italian Electrotechnical and Electronic Society (AEI) and the Editorial Board of Analog Integrated Circuits and Signal Processing.     

A Prototype Bandpass Sigma-Delta Modulator Employing Crystal Resonator

This paper describes an initial work on a second-order bandpass Sigma-delta modulator employing crystal resonator. The aim of this work is to explore the possibilities of realizing bandpass sigma-delta modulator using non-electronic resonators, such as micro-mechanical resonators. The initial study is based on crystal resonators as they have similar characteristics as the other types of resonator and are readily available. In order to obtain the desired loop transfer function, a compensation circuit is proposed to cancel the anti-resonance in the crystal resonator. The modulator chip is fabricated in a 0.6-μ m CMOS process. The bandpass noise shaping is demonstrated in the experiment with a 1- and 8-MHz crystal resonator, respectively. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R.China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. He is a Senior Member of IEEE. Xiaofeng Wang was born in Shangqiu, China, in 1980. He received B.Eng. degree from Northwestern Polytechnical University, Xi'an, China, in 2000 and M. Eng. degree from National University of Singapore, Singapore, in 2003, both in electrical engineering. He is currently working toward the Ph.D. degree at Tufts University, Medford, USA. His research is on high speed ADC design. Wai Hoong Sun was born in Taiping, Malaysia in 1976. He received the B. App. Sc. (Honours) degree in electrical engineering from the University of Toronto, Canada in 1999. After graduating, he joined Sharp Electronics Singapore as an R&D Engineer where he was involved in FPGA and digital IC design of display related circuits. In 2001 and 2002, he did full time research in the National University of Singapore on bandpass sigma-delta modulators. During that period, he was also a Graduate Tutor in electronics for second year electrical and computer engineering students. He then joined Philips Electronics Singapore in 2002 as a Lead Engineer. He did board-level designs for LCD and plasma televisions. He was also development project leader for a project that was successful in bringing to the market a range of LCD and plasma televisions. Currently, he is a Hardware Architect where he is responsible for the system-level electrical design of the television board.     

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm², and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he was with the NEC Information Technology Research Laboratories, Kawasaki, Japan, working on efficient implementations of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Sören Moch received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1997.Since then he has been Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of processor architectures for image, video and multimedia signal processing applications.Lars Friebe studied electrical engineering at the Universities Ulm and Hannover, Germany. In 1999, he worked at the NEC System ULSI Research Laboratory in Kanagawa, Japan. He received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1999.Since then he has been a Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of parallel programmable VLSI architectures for real-time image processing.Mark B. Kulaczewski started his studies in electrical engineering at the University of Hannover, Germany. In 1994, he transferred to Purdue University, West Lafayette, USA, and received the M.S. degree in electrical engineering in 1996.Since 1997 he has been a Research Assistant at the Laboratory for Information Technology and the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable real-time architectures for video coding and image segmentation, and instruction-set extensions for cryptographic applications.Sebastian Flügel was born in Crivitz, Germany, in 1975. He received his Dipl.-Ing. degree from the Department of Electrical Engineering of the University of Rostock in 2001.Since then he has been a Ph.D. candidate at the Institute of Microelectronic Systems at the University of Hannover. He works in the field of architectures and systems for video processing systems. His focus is on algorithms for video encoding and the development of optimized hardware architectures.Heiko Klußmann received the Dipl.-Ing. degree in computer engineering from the University of Hannover, Germany, in 2002.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests are in the area of programmable architectures for real-time video signal processing.Andreas Dehnhardt was born in Frankfurt am Main, Germany, in 1976. He received his Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 2002.Since then, he has been a Research Assistant with the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable architectures for multimedia applications and implementation of real-time MPEG-4 encoding schemes.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1980 and in Summer 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL research center, Stuttgart. Since 1987 he is Professor in the Department of Electrical Engineering, since 2002 in the Department of Computer Science at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002. His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

Thyristor Input-Protection Device Suitable for CMOS RF IC’s

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/45 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.Jin-Young Choi was born in Seoul, Korea in 1956. He received the B.S. degree in electrical engineering from the Seoul National University, Korea, in 1979, and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, USA, in 1986 and 1991, respectively. In 1991, he joined Samsung Electronics Memory Division, Korea, where he was engaged in high-speed SRAM development. In 1992, he moved to the Hongik University, Jochiwon, Korea, where he is now an associate professor. His recent research interests include the high-frequency modeling of CMOS devices, CMOS RF circuit design, and analysis & design for ESD protection.Woo Suk Yang was born in Seoul, Korea in 1957. He received the B.S. degree in electrical engineering from the Seoul National University, Korea, in 1979, and the Ph.D. degree in electrical and computer engineering from the North Calorina State University, USA, in 1990. His doctorial research was in the area of signal processing. In 1990, he joined LG Electronics Co. Korea. In 1991, he moved to the Hongik University, Jochiwon, Korea, where he is now a professor. His recent research interests include the high-frequency modeling and various topics in signal processing area.Dongmin Kim was born in Korea in 1956. He received the B.S. and M.S. degrees in electrical engineering from the Seoul National University, Korea, in 1979 and 1984, respectively and the Ph.D. degree in ECE from the University of Michigan, USA, in 1996. Now, he is an assistant professor of the Hongik University, Jochiwon, Korea. His recent research interests include circuit design and analysis.Youngju Kim was born in Seoul, Korea in 1957. He received the B.S. and M.S. degrees in electrical engineering from the Seoul National University, Korea in 1980 and 1985, respectively and the Ph.D. degree in electrical engineering from the Polytechnic University of New York, USA, in 1995, respectively. In 1996, he joined the Hongik University, Jochiwon, Korea, where he is now an assistance professor. His recent research interests include the RF circuit design and LIN wireless systems.