Input/Output Rail-to-Rail CMOS Operational Amplifier with Shaped Common-Mode Response

This paper presents an input/output rail-to-rail class-AB CMOS operational amplifier with reduced variations in unity-gain frequency over the entire voltage range. The rail-to-rail amplifier input stage is based on two parallel-connected complementary differential pairs. Variations in the small-signal response are kept to a minimum by realizing an adequate shaping of the CM response of the input stage, while still reducing deviations in the total limiting current of the two input pairs with respect to traditional solutions. This is achieved independently of the g _m -I _D characteristic of the amplifier input devices and of any strict matching condition between the complementary input pairs. Experimental results from a 3-V 0.8-m CMOS test-chip are given.     

An Adaptive Biased Single-Stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-<Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript> Input Stage

Using rail-to-rail (R-R) swing analog circuits has become almost mandatory in the design of low supply voltage circuits. In this paper, a new architecture for constant-g_m rail-to-rail input stages is presented. The design features a less than 5% deviation in g_m over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. By employing these techniques, a low-power operational amplifier (op-amp) with 100 MHz unity-gain bandwidth, 106 dB gain, 60^∘ phase margin, 2.65 V swing, and 6.4 nV/✓Hz input-referred noise with rail-to-rail input common-mode range is realized in a 0.8 μ m CMOS technology. This amplifier dissipates 10 mW from a 3 V power supply.     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

A Common Mode Feedback Structure for Differential OpAmps Using NMOS Depletion Transistors

A fully differential amplifier featuringa novel common mode feedback (CMFB) structure ispresented. Measurement results for the circuitmade in a 0.8 m process prove that the newstructure provides rail-to-rail common anddifferential mode input range that is difficultto handle for all active CMFB structures reportedso far. This improvement is accomplished by theuse of a nMOS depletion input pair transistorsthat can easily be processed in standard CMOStechnologies. The differential OpAmp is designedfor 3 V power supply and provides 61 dBamplification and a bandwidth of 24 MHz.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

Study of Fracture Mechanics in Testing Interfacial Fracture of Solder Joints

This paper is concerned with the mechanics of interfacial fracture that are active in two common testing configurations of solder joint reliability. Utilizing eutectic Pb-Sn/Cu as a reference system and assuming the presence of a predefined crack size in the intermetallic compound (IMC) layer, stress intensity factors (K _I and K _II) at the crack are numerically calculated for the two given configurations. The analysis of the tensile test configuration reveals that the fracture occurs by the crack-opening mode (K _I mode), as anticipated, but that it is greatly assisted by the viscoplasticity of the solder. With nonuniform viscoplastic deformation across the joint, K _I is found to increase much more rapidly than it would without the solder, decreasing the critical crack size to the micron scale. The same mechanism is also responsible for the development of a K _II comparable to K _I at the crack tip, that is, |K _I /K _II| ~ 1. It is also found that the predominant fracture mode in the bump shear configuration is crack opening, not crack shearing. This is an unexpected result, but numerical analyses as well as experimental observations provide consistent indications that fracture occurs by crack opening. During shear testing, bump rotation due to nonzero rotational moment in the test configuration is found to be responsible for the change in the fracture mode because the rotation makes K _I become dominant over K _II. With rotational moment being affected by the geometry of the bump, it is further found that the fracture behavior may vary with bump size or shape.     

Common-Mode Response Overlapping vs. Shaping in Rail-to-Rail Op-Amp Input Stages

In this paper, a circuit technique—common-mode (CM) response overlapping—for maintaining the small-signal behavior of rail-to-rail amplifiers nearly constant over the whole input CM range, is introduced. This technique modifies the CM response of the rail-to-rail input stage adequately by means of two constant input floating voltage sources, which are adjusted by using a static tuning section. Its performance is compared with a second technique—CM response shaping—, which is also based on two variable input floating voltage sources, but relies on a dynamic feedback tuning loop. Experimental results obtained from two 3-V 0.8-m CMOS single-stage rail-to-rail amplifiers, which operate with CM response overlapping and shaping, respectively, are provided.     

Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode

A family of compact CMOS rail-to-rail input stages with constant-g _m is presented. To attain a constant-g_m over the whole common-mode input range, an electronic zener diode is inserted between the tails of the complementary input pairs. This zener keeps the sum of the gate-source voltages of the input pairs, and therefore the g _m of the rail-to-rail input stage, constant. Two possible implementations of the zener have been realized and inserted in a rail-to-rail input stage. These input stages are implemented in two two-stage compact amplifiers. Both amplifiers have been realized in a 1 μm BiCMOS process. They have a unity-gain frequency of 2-MHz, for a capacitive load of 20 pF     

CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage

Two 3.3-V operational amplifiers with constant-g _m rail-to-rail input stage and rail-to-rail output stage are presented. The constant transconductance (g _m ) ensures a constant unity-gain frequency within the whole commonmode input range. Two new methods to control theg _m are introduced. Both operational amplifiers use the same rail-to-rail output stage. The operational amplifiers have been integrated in a CMOS semicustom process with transistor lengths of 10µm. The common-mode input voltage swing extends beyond the positive supply rail by 400 mV and beyond the negative supply rail by 200 mV. The output voltage is able to reach within 130 mV of the supply rails. The output current of the operational amplifiers is 2 mA and the voltage gain is 85 dB. The unity-gain frquency is 165 kHz, which is mainly limited by the relatively long transistor lengths of 10µm. In another process with channel lengths of 2µm, simulation results showed that a unity-gain frequency of 4 MHz can easily be obtained.     

Temperature dependent current–voltage (I–V) characteristics of Au/n-Si (1 1 1) Schottky barrier diodes with PVA(Ni,Zn-doped) interfacial layer

Current–voltage (I–V) characteristics of Au/PVA/n-Si (1 1 1) Schottky barrier diodes (SBDs) have been investigated in the temperature range 80–400 K. Here, polyvinyl alcohol (PVA) has been used as interfacial layer between metal and semiconductor layers. The zero-bias barrier height (Φ_B0) and ideality factor (n) determined from the forward bias I–V characteristics were found strongly dependent on temperature. The forward bias semi-logarithmic I–V curves for different temperatures have an almost common cross-point at a certain bias voltage. The values of Φ_B0 increase with the increasing temperature whereas those of n decrease. Therefore, we have attempted to draw Φ_B0 vs. q/2kT plot in order to obtain evidence of a Gaussian distribution (GD) of the barrier heights (BHs). The mean value of BH and standard deviation (σ₀) were found to be 0.974 eV and 0.101 V from this plot, respectively. Thus, the slope and intercept of modified vs. q/kT plot give the values of and Richardson constant (A^?) as 0.966 eV and 118.75 A/cm²K², respectively, without using the temperature coefficient of the BH. This value of A^* 118.75 A/cm²K² is very close to the theoretical value of 120 A/cm²K² for n-type Si. Hence, it has been concluded that the temperature dependence of the forward I–V characteristics of Au/PVA/n-Si (1 1 1) SBDs can be successfully explained on the basis of the Thermionic Emission (TE) theory with a GD of the BHs at Au/n-Si interface.     

Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I DDQ Testing

The effectiveness of single threshold I _DDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta I _DDQ is identified as one alternative for deep submicron current measurements. Often delta I _DDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the I _DDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate I _DDQ limits for normal and stressed operating conditions of 0.18 m n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed I _DDQ testing is also investigated.     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

Incorporating I DDQ Testing with BIST for Improved Coverage: An Experimental Study

In this paper we present an experimental study on the effectivenessof incorporating at-speed I _DDQ testing with traditionalBIST for improved test coverage. The high speed I _DDQtesting is conducted using the differential built-in on-chip current sensor(BICS) that we have recently developed. Two test chips were designed andfabricated implementing a CMOS version of the 74181 ALU chip. In copies ofthis circuit we included the capability of activating 45 differentrealistic CMOS faults: inter- and intra-layer shorts andopens. We examine the fault coverage of both Boolean (voltage) testing andI _DDQ testing for these realistic faults. An interestingfinding of our study is that I _DDQ testing also detectedseveral of the open faults. Moreover, these include precisely those openfaults for which two pattern voltage tests can get invalidated because oftransient switching states. Our results show that combining both Boolean andcurrent testing does enhance test coverage in a BIST environment.     

Low-Voltage Differentiator for VHF Filtering

In this paper a G _m -C resonator circuit is proposed which is based on a new current-mode differentiating concept, compatible with low voltage and very high frequency operation.A prototype 4th-order 200 MHz band pass filter has been fabricated using a 0.8 m CMOS process and shows a side-band rejection lower than –80 dB. This response confirms the feasibility of the proposed resonator in very-high frequency applications such as IF band pass sections of RF front-end circuits. The filter consumes less than 5.5 mW from a 2.7 V supply and the measured dynamic range is 57 dB at IM3 of 0.5%, where the active area is 0.12 mm².     

Pure-Mode Gm−C Biquad Filters*

A continuous time differential voltage mode G_m–C biquad and its adjoint current-mode version are described, employing FCS (floating current source) circuits as building blocks. The biquad operates in the pure mode, i.e. no resistors are used to convert internally voltage into current or vice versa. Both f_p and Q_p are tunable by current sources applied externally. The current mode version is capable of providing values of Q_p 160. Due to the increasing Loop transmission, THD improves significantly towards low frequencies. The input stage of the voltage mode version employs two OTAs, whose outputs are connected in parallel in order to add their differential inputs. This results in the hitherto unnoticed property of subtracting their common mode input, providing an open loop gain which is high for differential, but low for common mode signals.     

Optimising operational amplifiers by evolutionary algorithms and gm/Id method

The evolutionary algorithm called non-dominated sorting genetic algorithm (NSGA-II) is applied herein in the optimisation of operational transconductance amplifiers. NSGA-II is accelerated by applying the g_m/I_d method to estimate reduced search spaces associated to widths (W) and lengths (L) of the metal-oxide-semiconductor field-effect-transistor (MOSFETs), and to guarantee their appropriate bias levels conditions. In addition, we introduce an integer encoding for the W/L sizes of the MOSFETs to avoid a post-processing step for rounding-off their values to be multiples of the integrated circuit fabrication technology. Finally, from the feasible solutions generated by NSGA-II, we introduce a second optimisation stage to guarantee that the final feasible W/L sizes solutions support process, voltage and temperature (PVT) variations. The optimisation results lead us to conclude that the g_m/I_d method and integer encoding are quite useful to accelerate the convergence of the evolutionary algorithm NSGA-II, while the second optimisation stage guarantees robustness of the feasible solutions to PVT variations.     

Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.     

On the geometrical dependence of low-frequency noise in SiGe HBTs

We present an investigation of the dependence of low-frequency noise on device geometry in advanced npn silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs). The devices examined in this work have fixed emitter width (W_E = 0.4 μm), but varying emitter length (0.5 μm  L_E  20.0 μm), and thus the ratio of the emitter perimeter (P_E) to the emitter area (A_E) varies widely, making it ideal for examining geometrical effects. The SPICE noise parameter A_F extracted from these devices decreases with increasing L_E. Furthermore, the low-frequency noise measured on SiGe HBTs with significantly different P_E/A_E ratios suggests a possibility that the fundamental noise source for the diffusion base current may be located at the emitter periphery. Transistors with different distances between the emitter edge and the shallow trench edge (XEC), and shallow trench edge to deep trench edge (XTC), are also investigated. The SiGe HBTs with a smaller value of XEC have higher low-frequency noise, but no significant difference is found in devices with varying XTC. Explanations of the observed noise behavior are suggested.     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.