InP/InGaAs HBTs with n+-InP contacting layers grown byMOMBE using SiBr4

InP/InGaAs heterojunction bipolar transistors (HBTs) with low resistance, nonalloyed TiPtAu contacts on n⁺-InP emitter and collector contacting layers have been demonstrated with excellent DC characteristics. A specific contact resistance of 5.42×10^-8 Ω·cm², which, to the best of our knowledge, is the lowest reported for TiPtAu on n-InP, has been measured on InP doped n=6.0×10¹⁹ cm^-3 using SiBr₄. This low contact resistance makes TiPtAu contacts on n-InP viable for InP/InGaAs HBTs     

InAlAs/InGaAs/InP HFET with suppressed impact ionization usingdual-gate cascode-devices

InAlAs/InGaAs dual-gate-HFETs (DGHFETs) and single-gate-HFETs (SGHFETs) have been fabricated and characterized with special emphasis on reducing the impact ionization. For the first time it is shown that in the case of the DGHFET, due to the second gate (V_G2S=0 V), impact ionization can be totally prevented in the channel underneath the RF-driven gate without reduction of the RF-relevant parameters such as transconductance, output resistance and voltage gain. The electric field and the potential distribution in the channel are discussed using a nomogram and confirmed by 2-D simulation. According to V_G2S=0 V, a new cascode design is presented by directly connecting the second gate to the source (ground)     

Impact ionization and transport in the InAlAs/n+-InPHFET

We have carried out an experimental study exploring both impact ionization and electron transport in InAlAs/n⁺-InP HFET's. Our devices show no signature of impact ionization in the gate current, which remains below 17 μA/mm under typical bias conditions for L_g=0.8 μm devices (60 times lower than for InAlAs/InGaAs HEMT's). The lack of impact ionization results in a drain-source breakdown voltage (BV_DS) that increases as the device is turned on, displaying an off-state value of 10 V. Additionally, we find that the channel electron velocity approaches the InP saturation velocity of about 10⁷ cm/s (in devices with L_g<1.6 μm) rather than reaching the material's peak velocity. We attribute this to the impact of channel doping both on the steady-state peak velocity and on the conditions necessary for velocity overshoot to take place. Our findings suggest that the InP-channel HFET benefits from channel electrons which remain cold even at large V_GS and V_DS making the device well-suited to power applications demanding small I_G, low g_d, and high BV_DS     

Physics of breakdown in InAlAs/n+-InGaAs heterostructurefield-effect transistors

InAlAs/n⁺-InGaAs HFET's on InP have demonstrated a high breakdown voltage in spite of the narrow bandgap of the InGaAs channel. In order to understand this unique feature, we have carried out a systematic temperature-dependent study of off-state breakdown. We find that off-state breakdown at room-temperature is drain-gate limited and that the breakdown voltage shows a negative temperature coefficient. Based on these and other findings, we propose that off-state breakdown is a two-step process. First, electrons are injected by thermionic-field emission from the gate to the insulator. Second, electrons enter into the high-field drain-gate region of the channel hot, and relax their energy through impact-ionization. This combined mechanism explains our experimental observations that off-state breakdown in InAlAs/n⁺ -InGaAs HFET's depends both on channel and insulator design. Our findings are relevant to other InAlAs/InGaAs HFET's, such as the MODFET, as well as HFET's based on other narrow-bandgap materials     

A high-performance InGaAs/InAlAs double-heterojunction bipolartransistor with nonalloyed n+-InAs cap layer on InP(n) grownby molecular beam epitaxy

An InGaAs/InAlAs double-heterojunction bipolar transistor (DHBT) on InP(n) grown by molecular-beam epitaxy (MBE) that exhibits high DC performance is discussed. An n⁺-InAs emitter cap layer was used for nonalloyed contacts in the structure and specific contact resistances of 1.8×10^-7 and 6.0×10^-6 Ω-cm² were measured for the nonalloyed emitter and base contacts, respectively. Since no high-temperature annealing is necessary, excellent contact surface morphology on thinner base devices can easily be obtained. In devices with 50×50-μm² emitter area, common-emitter current gains as high as 1500 were achieved at a collector current density of 2.7×10³ A/cm² . The current gain increased up to 2000 for alloyed devices     

n+-p-p+structure InP solar cells grown by organometallic vapor-phase epitaxy

The fabrication of n⁺-p-p⁺InP solar cells by OMVPE has been studied. A conversion efficiency (active area) as high as 20 percent under AM1.5 illumination has been obtained. It is experimentally verified that the n⁺-p-p⁺InP solar cell has a higher resistance to radiation degradation than the n⁺-p InP solar cell. Diode characteristics and photovoltaic performances such as saturation current density, diode-ideality factor, and open-circuit voltage for the n⁺-p-p⁺cells are found to drastically deteriorate when junction depth decreases to ≤ 0.15 µm. An electron concentration dependence of a hole diffusion length in n-InP is estimated from the measurement of photoluminescence spectra. For the improvement of photovoltaic performances, a series of systematic examinations has been made on the relationship between collection efficiency and hole diffusion length from photogenerated carrier distribution analysis.     

Spectral response of n+-n-p and n+-p photodiodes

Results of calculations for the quantum efficiency of three different types of n⁺-p, n⁺-n-p, and OCI-HLE diodes are reported. Exact numerical modeling of current density equations, modified to include bandgap reduction and Auger recombination is used to compute the quantum efficiency of these diodes. It is found that an optimized n⁺-p structure can result in over all spectral response comparable to the n⁺-n-p structure, although it is not as good as that of the OCI-HLE type of diodes. Further, these calculations show that one can achieve low dark current in these diodes, but at the expense of lower quantum efficiency particularly for wavelengths less than 0.4 µm.     

Doubly strainedIn0.41Al0.59As/n+-In0.65Ga0.35As HFET with high breakdown voltage

An In_0.41Al_0.59As/n⁺-In_0.65 Ga_0.35As HFET on InP was designed and fabricated, using the following methodology to enhance device breakdown: a quantum-well channel to introduce electron quantization and increase the effective channel bandgap, a strained In_0.41Al_0.59As insulator, and the elimination of parasitic mesa-sidewall gate leakage. The In_0.65Ga_0.35As channel is optimally doped to N_D=6×10¹⁸ cm^-3. The resulting device (L_g=1.9 μm, W_g =200 μm) has f_t=14.9 GHz, f_max in the range of 85 to 101 GHz, MSG=17.6 dB at 12 GHz V_B=12.8 V, and I_D(max)=302 mA/mm. This structure offers the promise of high-voltage applications at high frequencies on InP     

Carrier distribution and low-field resistance in short n+-n--n+and n+-p--n+structures

In the present paper, we calculate the potential, field, and carrier distributions in short n⁺-n^--n⁺and n⁺-p^--n⁺devices and estimate the low-field resistance. The results of the calculations present a set of universal curves which may be used to find the minimum carrier density in the sample, the barrier height, the electric field at the boundary, etc. Our calculations show that electron injection becomes very important when the doping level is smaller than 1.5 × 10¹⁴(cm^-3). (T/300 K)/ L²(µm) for GaAs diodes, whereLis the sample length. The low-field resistance of the sample is limited by the thermionic emission of the sample and by the diffusion and drift in the sample. The thermionic emission dominates at low temperatures, in short samples, and the diffusion-drift dominates in longer samples at higher temperatures. The experimental values of low-field resistance for GaAs 0.4-µm n⁺-n^--n⁺devices at 77 and 300 K are in good agreement with the predicted values. The agreement is not so good for 0.25-µm devices and for n⁺-p^--n⁺devices. In the latter case, the disagreement may be due to uncertainty in the doping level because the low-field resistance of the n⁺-p^--n⁺structure is shown to be very sensitive to the doping level of the p-region.     

A new self-aligned recessed-gate InP MESFET

We describe a new self-aligned recessed-gate InP MESFET. In this structure, material selective and anisotropic etching properties of InP/InGaAsP system are utilized to alleviate the difficulties associated with channel recess and gate alignment. Using this technique a 1-µm Al-gate InP MESFET with a transconductance ∼ 110 mS/mm is demonstrated.     

Corner currents in p+-n-n+diodes with n+isolation diffusions

The magnitude of corner currents in rectangular diffused p⁺-n-n⁺diodes with deep n⁺isolation diffusions is discussed. Curves are given to illustrate the importance of this current in diodes and IIL structures.     

A model of front-illuminated n+-p-p+high-efficiency silicon solar cell

A realistic model of a front-illuminated n⁺-p-p⁺ silicon solar cell is developed by solving the current continuity equations for minority carriers in the quasi-neutral regions in steady state, assuming the light in the cell is trapped as a result of multiple reflections at the front and the back of the cell. This model is used to study the effects of the front emitter thickness and doping level and the light trapping on the J-V characteristic and thereby on the open-circuit voltage, short-circuit current density, curve factor, and the efficiency of the cell. A textured cell with an emitter thickness in the range of 0.3-1.0 μm with its doping ≈5×10¹⁸ cm^-3 and the recombination velocities of minority carriers as large as 200 cm/s at the n⁺ front surface and 10 cm/s at the back of the p base can exhibit an efficiency in excess of 26% (under AM 1.5 sunlight of 100 mW/cm² intensity) at 25°C if the light reflection losses at the front surface can be made small     

n+-polysilicon gate PMOSFET's with indium dopedburied-channels

In this letter a n⁺-polysilicon gate PMOSFET with indium doped buried-channel is discussed, The gate length scaling of n ⁺-polysilicon gate buried-length PMOSFET's is limited by the channel punch-through effect. Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effects in these devices. Indium, an acceptor dopant in Si, has a low diffusion coefficient and implant statistics favorable for achieving shallow doping layers. Indium implants are explored (as an alternative to BF₂) to counter dope the n-tub for adjusting the threshold voltage. Devices are fabricated using AT&T's 0.5 μm CMOS technology but with t_ox=50 Å. Although no special effort has been made to optimize the n-tub or to take full advantage of the diffusion and implant characteristics of indium, excellent electrical results are obtained for devices with L_eff=0.25 μm. Improved V_th roll-off characteristics and reduced body effect (γ≈0.18 V^½ versus γ_B≈0.40 V^½) in indium implanted buried channels are demonstrated over BF₂ implanted buried channels for PMOSFET's with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states on the electrical device characteristics are demonstrated by device simulations and measurements     

Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing     

Noise in short n+-n--n+GaAs diodes

Noise measurements in a short, near-ballistic, n⁺-n^--n⁺GaAs diode are reported. The device had a linear characteristic below 100 mA. It showed1/fnoise at low frequencies and a white noise close to the thermal noise of the device conductancegat high frequencies. The1/fnoise is most likely mobility fluctuation noise; we evaluated Hooge's parameter α and found a value of 1.95 × 10^-6at room temperature and 0.959 × 10^-6at liquid nitrogen temperature. We also observed a1/fnoise spectrum turning over into1/f^0.5spectrum at 77 K.     

InGaAs(InAlAs)/InP和InP/InAlAs湿法选择腐蚀研究

介绍了两种选择腐蚀液对InGaAs(InAlAs)I/nP和InPI/nAlAs异质结构材料选择腐蚀的实验结果,重点介绍在InAlAs上面生长InP的湿法选择腐蚀,用HClH∶3PO4C∶H3COOH系列腐蚀液,InPI/nAlAs选择比大于300。InPI/nAlAs湿法选择腐蚀的结果可以很好应用到OEIC芯片制作中,并取得了较好的器件及电路结果。     

InP/InAlAs/InGaAs quantum wires

Single InGaAs quantum wires and stacked InGaAs quantum wires with InAIAs barriers have been fabricated on V-grooved InP substrates by low pressure metal-organic chemical vapour deposition (MOCVD). We have found growth conditions where the InAIAs barrier exhibits a resharpening effect, similar to that of AlGaAs utilized for growth on GaAs substrates. The existence of structural and electronic quantum wires in the bottom of the grooves is proven.     

InGaAs（InAIAs）／InP和InP／InAIAs湿法选择腐蚀研究

介绍了两种选择腐蚀液对InGaAs（InAlAs）／InP和InP／InAlAs异质结构材料选择腐蚀的实验结果，重点介绍在InAlAs上面生长InP的湿法选择腐蚀，用HCl：H3PO4：CH3COOH系列腐蚀液，InP／InAlAs选择比大于300。InP／InAlAs湿法选择腐蚀的结果可以很好应用到OEIC芯片制作中，并取得了较好的器件及电路结果。     

Polyoxides grown on n+ polysilicon

The polarity asymmetry on the electrical characteristics of the oxides grown on n⁺ polysilicon (polyoxides) was investigated in terms of the oxidation process, the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that the thin polyoxide prepared by using a low-temperature wafer loading and N₂ pre-annealing process, has a smoother polyoxide/polysilicon interface and exhibits a lower oxide tunneling current, a higher dielectric breakdown field when the top electrode is positively biased, a lower electron trapping rate and a larger charge-to-breakdown than does the normal polyoxide. The polarity asymmetry is also strongly dependent on the doping level of the lower polysilicon layer, the oxidation temperature and the oxide thickness. It was found that only the thinner polyoxides (⩽240 Å) grown on the heavily-doped polysilicon film (30 Ω/sq) by using the higher-temperature oxidation process (⩾950°C) conduct a less oxide tunneling current when the top electrode is positively biased