12bit高稳定性数模转换器设计

设计了一款12 bit高稳定性控制类数模转换器(DAC),该DAC集成了带有稳定启动电路的新型低失调带隙基准源(BGR),改善了基准电路的稳定性以及对温度和工艺的敏感性;DAC采用了改进的两级电阻串结构,通过开关电阻匹配和特殊版图布局,在既不增加电路功耗又不扩大版图面积的前提下,提高了DAC的精度并降低了工艺浓度梯度对整体性能的影响.基于CSMC 0.5 μm 5 V 1P4M工艺对所设计的DAC芯片进行了流片验证.测试结果表明:常温下DAC的微分非线性(DNL)小于0.45 LSB,积分非线性(INL)小于1.5 LSB,并且在-55～125℃内DNL小于1 LSB,INL小于2.5 LSB;5V电源电压供电时功耗仅为3.5 mW,实现了高精度、高稳定性的设计目标.     

一种GSM无线发射系统中的低功耗数模转换器

针对GSM标准无线发射系统中数模转换器(DAC)的要求,分析了影响其性能和功耗的限制因素,并在SMIC 0·13μm CMOS工艺1.2 V电源电压下设计了一款10位电流驱动型数模转换器(Current-steering DAC).使用最佳拟合线的算法衡量电流源匹配的随机误差对DAC静态非线性的影响,使得DAC的电流源...     

An efficient tool for the assisted design of SAR ADCs capacitive DACs

The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic capacitance effects in the feedback charge redistribution DAC. Since both contributions depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical environment to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances computing both differential and integral nonlinearity (DNL, INL). An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 10⁴ shorter simulation time, allowing statistical simulations that would be otherwise impracticable. The switching energy and SNDR degradation due to static nonlinear effects are also estimated. Simulations and measurements on three designed and two fabricated prototypes confirm that the proposed tool can be used as a valid instrument to assist the design of a charge redistribution SAR ADC and to predict its static and dynamic metrics.     

A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters

In this paper, we propose a reconfigurable current-steering digital-to-analog converter (DAC). The differential nonlinearity error (DNL) of the DAC is estimated on-chip. This is used to reconfigure the switching sequence to get a lower integral nonlinearity error (INL). We propose a novel technique for estimation of DNL based on a step-size measurement. This greatly reduces the linearity and dynamic range requirements of the measuring circuits. A 10-b segmented DAC, along with the associated circuits for DNL estimation and reconfiguration, was designed using 0.35-/spl mu/m CMOS technology and fabricated through Europractice. The paper includes theoretical analysis, simulation, and experimental results for the proposed technique.     

一种用于14 bit SAR ADC的DAC设计

本文设计了用于14bit逐次逼近型模数转换器（SAR ADC）的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL〈0.5LSB,DNL〈0.6LSB。仿真结果表明,本DAC设计极大改善SAR ADC的性能,已达到设计要求。     

基于QN旋转布局的10位500 MS/s分段电流舵DAC

针对分段电流舵数/模转换器（Digital-to-Analog Converter，DAC），通过理论分析和推导，研究电流源阵列系统失配误差和寄生效应对非线性的影响，采用电流源阵列Q^N旋转游走版图布局方案，能够减小电流源系统失配的一次误差，而且版图布线简单，由寄生效应引起的电流源失配较小，利于DAC非线性的优化.基于0.18μm CMOS，采用"6+4"的分段结构，设计了一种10位500MS/s分段电流舵DAC，流片测试结果表明，在输入频率为1.465MHz，采样速率为500MS/s的条件下，无杂散动态范围（Spurious Free Dynamic Range，SFDR）为64.9dB，有效位数（Effective Number of Bits，ENOB）为8.8 bit，微分非线性误差（Differential Non-linearity，DNL）和积分非线性误差（Integral Non-linearity，INL）分别为0.77LSB和1.12LSB.     

一种10位电容电阻混合型双极性D/A转换器

在加速度计中,需要数模转换器(DAC)提供一个稳定的偏压来消除重力加速度,要求DAC具有高精度、单调性和小面积等特性。为了解决传统电阻型DAC存在的大面积和传统电容DAC中存在的非单调性等问题,提出了一种电容电阻混合型DAC结构,并设计了一个10位的DAC,用于提供稳定偏压。提出一种新的电容共质心的版图布局,提高了DAC的精度。该DAC在0.5μm CMOS工艺上得以验证实现,微分非线性误差(DNL)最大为0.50LSB,积分非线性误差(INL)最大为0.82LSB,在5V和-5V的双电源供电条件下,芯片功耗为16mW,完全满足了工程需求。     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

Nonlinearity analysis of folded Multi-LSB decided resistor string digital to analog converter

A theoretical nonlinearity analysis of folded multi-LSB decided resistor string DAC is presented. By the derived theoretical equations, circuit designers can calculate the required resistor mismatch very quickly, thus reducing the design time. The Monte-Carlo simulation results agree well with the theoretical equations and confirm their accuracy.     

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs

This paper describes a new Built-In-Self-Test(BIST) scheme for estimation of static non-linearity errors in segmented and binary weighted digital to analog converters (DACs). The BIST scheme comprises of a hierarchy of tests including tests for non-monotonicity, checks to detect if the DNL/INL errors exceed ±0.5 LSB and actual estimation of the DNL/INL. The BIST scheme has been experimentally verified on 10-bit segmented current steering DAC. The DAC, along with the additional circuits required for testing, was designed and fabricated using a 0.35 m process. Both simulation and experimental results are included in this paper. Errors estimated using the BIST scheme match well with measurements done on the fabricated device.     

A 12-bit 0.35 μm CMOS area optimized current-steering hybrid DAC

In this paper a 12-bit current-steering hybrid DAC is implemented using AMS 0.35 μm CMOS process technology. The architecture and design methodology used for the implementation of the DAC offer advantages like design speed up, easiness in design and a small active area. The proposed hybrid DAC consists of four 3-bit parallel matched current-steering subDACs and resistive networks that properly weight the current output of each subDAC to obtain the overall voltage-mode output of the 12-bit hybrid DAC. The performance of the hybrid DAC is validated through static and dynamic performance metrics. Simulations indicate that the DAC has an accuracy of 12-bit and a SFDR higher than 66 dB in whole Nyquist frequency band. The simulated INL is better than 1 LSB, while simulated DNL is better than 0.25 LSB. At an update rate of 250 MS/s the SFDR for signals up to 10 MHz is higher than 66 dB. The Figure of Merit (FoM) of the implemented hybrid DAC is better than recently presented DACs with 12-bit resolutions and implemented using various process technologies. The proposed hybrid DAC supporting high update rates with good dynamic performance can be used as an alternative in various applications in industry including video, digital TV, cable modems etc.     

Design of low-power ROM-less direct digital frequency synthesizerusing nonlinear digital-to-analog converter

A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies     

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

Based on a 5 MSBs(most-significant-bits)-plus-5 LSBs(least-significant-bits) C-R hybrid D/A conversion and low-offset pseudo-differential comparison approach,with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method,an 8-channel 10-bit 200-kS/s SAR ADC(successive-approximation -register analog-to-digital converter) IP core for a touch screen SoC(system-on-chip) is implemented in a 0.18μm 1P5M CMOS logic process.Design considerations for the touch sc...     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

Nonlinearity analysis of double multi-bit decided folded resistor string digital-to-analog converter

This paper presents a double multi-bit decided folded resistor string digital-to-analog converter that notably reduces the number of output voltage nodes compared with the conventional resistor string digital-to-analog converter. A theoretical nonlinearity analysis of the newly proposed topology based on random, zero-mean, and normally distributed resistor mismatches is also presented. The derived equations enable circuit designers to quickly select the most suitable design for their applications by calculating the required resistor mismatch. Monte-Carlo simulation results show strong agreement with theoretical equations and confirm their accuracy.     

Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch

This brief analytically investigates the digital-analog converter (DAC) integrated nonlinearity (INL) with respect to the accuracy of the DAC unit elements. The main novelty of the presented approach is in the application of the Brownian Bridge (BB) process to precisely describe the INL. This method analyzes the thermometer and binary DAC architectures and is the first to prove that their statistical INL properties are different. The INL of the thermometer DAC is represented as a one-dimensional BB process. For the binary case, the INL is represented as combinations of random variables, the increments of which coincide with a BB process. For both architectures, this brief derives formulas for the INL main statistical properties, e.g., probability density function, mean, deviation, and chip yield. These properties are compared with previous analytical attempts and conclusions are drawn. The results of this brief fill a gap in the general understanding of the most quoted DAC specification- the INL. In particular, for a high-volume chip production, the derived formulas will help engineers to choose the DAC architecture and the allowed mismatch of the DAC unit elements     

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within ±0.25 LSB at 15 b, and the INL was measured to be within ±1.25 LSB at 15 b. The die area is 9.3 mm×8.3 mm and operates on ±4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4-μm BiCMOS process     

BIST structure for DAC testing

A built-in self-test (BIST) structure for digital-to-analogue converter (DAC) testing is presented. The basic idea is to divide the input codes (0, 1, ..., 2ⁿ-1) of the DAC under test into a number of segments. The DAC output voltages corresponding to different codes in the same segment are amplified to the same voltage value. Such that one single reference voltage can be used to test all codes in the same segment. By this method, the number of reference voltages required for DAC testing can be greatly reduced. We show that offset error, gain error, integral nonlinearity (INL) and differential nonlinearity (DNL) are effectively detected in the proposed BIST structure     

A 10-Bit 500-MS/s 55-mW CMOS ADC

A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a high-speed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55$~$mW from a 1.2-V supply.      

Nonlinearity correction for multibit /spl Delta//spl Sigma/ DACs

This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.