A CMOS RF front-end for a multistandard WLAN receiver

This letter describes the design and performance of a dual band tri-mode receiver front-end compliant with the IEEE 802.11a, b, and g standards. The receiver front-end was built in a 0.18-/spl mu/m CMOS process and achieves a noise figure of 4.7 dB/5.1 dB for the 2.4-GHz/5-GHz bands, respectively. The receiver front-end provides a dual gain mode of 5 dB/30 dB with an IIP3 of -1dBm for the low gain mode. The front-end draws 25 mA/27 mA from a 1.8-V supply for the 2.4-GHz/5-GHz bands, respectively.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 μm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology

A 3.1-4.8 GHz ultra-wideband (UWB) receiver front-end for high data rate, short-range communication is presented. The receiver, based on the Multi Band OFDM Alliance (MBOA) standard proposal, consists of a zero-IF receive chain and an ultra-fast frequency-hopping synthesizer. The combination of high-linearity RF circuits, aggressive baseband filtering and low local oscillator spurs from the synthesizer results in an interference-robust receiver, having the ability to co-exist with systems operating in the 2.4-GHz and 5-GHz ISM bands. The packaged device shows an overall noise figure of 4.5 dB and has a measured input IP3 of -6 dBm and input IP2 of +25 dBm. Spurious tones generated by the synthesizer are below -45 dBc and -50 dBc in the 2.4-GHz and 5-GHz ISM bands, respectively. The hopping speed is well below the required 9.5 ns. The complete receive chain has been realized in a 0.25 /spl mu/m BiCMOS technology and draws 78mA from a 2.5-V supply.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

A tri-mode Compass/GPS/Galileo RF receiver with all-digital automatic gain control loop

A tri-mode RF receiver with all digital automatic gain control (AGC) loop and non-uniform 2-bit analog-to-digital converter (ADC) is designed for the bands of GPS-L1, Galileo-E1 and Compass B1 in 0.18 μm CMOS process. The RF front-end, analog baseband and frequency synthesizer with voltage controlled oscillator (VCO) have been integrated, and there are only few off-chip components including bypass capacitances, matching network and TCXO. For anti-jamming consideration, an all digital AGC loop with relevant variable gain amplifier (VGA) and non-uniform ADC is implemented to suppress interference and avoid saturation of signal chain. While drawing 35 mA current, this receiver achieves a total noise figure of 4 dB and a maximum gain of 105 dB, with a die area of 2.4 × 2.4 mm².     

A 2.4-GHz sub-mW CMOS receiver front-end for wireless sensors network

A 2.4-GHz fully integrated CMOS receiver front-end using current-reused folded-cascode circuit scheme is presented. A configuration utilizing vertically stacked low-noise amplifier (LNA) and a folded-cascode mixer is proposed to improve both conversion gain and noise figure suitable for sub-mW receiver circuits. The proposed front-end achieves a conversion gain of 31.5dB and a noise figure of 11.8dB at 10MHz with 500-/spl mu/A bias current from a 1.0-V power supply. The conversion gain and noise figure improvements of the proposed front-end over a conventional merged LNA and single-balanced mixer are 11dB and 7.2dB at 10MHz, respectively, with the same power consumption of 500/spl mu/W.     

Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P_-1 dB)(P_{{-1}\,{\rm dB}}) of −13.5 dBm and the input-referred third-order intercept point (P _IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 ×0.721.45 \times 0.72 mm² including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.     

A 5.25-GHz image rejection RF front-End Receiver With Polyphase filters

A 5.25-GHz image rejection (IR) radio frequency (RF) front-end receiver is proposed, which is implemented in 0.18-/spl mu/m CMOS technology. The proposed receiver adopts both a high-intermediate frequency (IF) and the double quadrature architecture to achieve high IR at 5-GHz frequency. The measured results show a power gain of 14 dB, a minimum noise figure of 7.9dB, and IIP3 of -8dBm. The measured maximum image rejection ratio is 45dBc. The receiver consumes a total of 32mA from a 1.8-V supply.     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network

In this paper, we present a receiver front-end and a frequency source suitable for wireless sensor network applications, in which power consumption is severely restricted under several milliwatts. For such an extremely low-power receiver, current-reusing and frequency multiplying schemes are proposed for both the RF front-end and frequency source. The proposed front-end achieves a conversion gain of 30.5 dB and a noise figure of 10.2 dB at the 10-MHz intermediate frequency (IF), taking only 500-muA bias current from a 1.0-V supply voltage. The measured phase noise of the fabricated frequency source is -115.83 dBc/Hz at 1 MHz offset from a 2.2-GHz center frequency, taking 840 muA from a 0.7-V supply. The front-end performance is compared with the previously reported low-power front-ends operating in similar frequency ranges     

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A WiMedia/MBOA compliant RF transceiver for ultra-wideband data communication in the 3-5-GHz band is presented. The transceiver includes receiver, transmitter and synthesizer is completely integrated in 0.13-mum standard CMOS technology. The receiver uses a feedback-based low-noise amplifier (LNA) to obtain an RF gain of 4 to 37 dB and an overall measured noise figure of 3.6 to 4.1 dB over the 3-5-GHz band of interest. The transmitter supports an error vector magnitude (EVM) of -28 dB up to -4 dBm output power and meets the FCC and WiMedia mask specifications. The power consumption from a single supply voltage of 1.5 V is 237 mW for the receiver and 284 mW for the transmitter, both including the synthesizer     

A 5-GHz highly integrated receiver front-end

In this paper a radio front-end for a IEEE 802.11a and HIPERLAN2 sliding-IF receiver is presented. The circuit, implemented in a low-cost 46-GHz-f _T silicon bipolar process, includes a variable-gain low noise amplifier and a double-balanced mixer. Thanks to monolithic LC filters and on-chip single-ended-to-differential conversion of the RF signal, the proposed solution does not require the expensive image rejection filter and an external input balun. The receiver front-end exhibits a 4.3-dB noise figure and a power gain of 21 dB, providing an image rejection ratio higher than 50 dB. By using a 1-bit gain control, it achieves an input 1-dB compression point of −11 dBm, while drawing only 22 mA from a 3-V supply voltage.     

A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of −95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of −76 and −79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.     

Image-rejection receiver using on-chip active notch filters for 2.4-GHz band wireless communication applications

This paper presents the design and experimental results of image-rejection (IR) receiver front-end for 2.4-GHz band applications. The proposed IR-receiver front-end integrates a third-order active notch filter into each of conventional cascode low noise amplifier and down-conversion mixer to achieve high image-rejection ratio (IRR). The image signal is suppressed and the wanted signal is maximized due to series and parallel resonator effects of the notch filter, respectively. Consequently, the proposed IR-receiver front-end implemented in a standard 0.18 μm CMOS technology has the power gain of 21.5 dB, the noise figure of 3.5 dB, the input third order intermodulation product of ?15 dBm and the IRR of 56 dB. The IR-receiver front-end dissipates a total of 5.5 mA from supply voltage of 1.8 V.     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.     

A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO

A low-voltage receiver front-end for 5-GHz radio applications is presented. The receiver consists of a low-noise amplifier (LNA) with notch filter, a voltage-controlled oscillator (VCO), and a mixer. The LNA/notch filter has an automatic Q-tuning circuit integrated with it to provide good image rejection. On-chip transformers are used extensively in the receiver to improve performance and facilitate low-voltage operation. The receiver has a gain of 19.8 dB, noise figure of 4.5 dB, a third-order input intercept point (IIP3) of -11.5 dBm, and an image rejection of 59 dB, and the VCO had a phase noise of -116 dBc/Hz at 1-MHz offset.     

A fully integrated 24-GHz eight-element phased-array receiver in silicon

This paper reports the first fully integrated 24-GHz eight-element phased-array receiver in a SiGe BiCMOS technology. The receiver utilizes a heterodyne topology and the signal combining is performed at an IF of 4.8 GHz. The phase-shifting with 4 bits of resolution is realized at the LO port of the first down-conversion mixer. A ring LC voltage-controlled oscillator (VCO) generates 16 different phases of the LO. An integrated 19.2-GHz frequency synthesizer locks the VCO frequency to a 75-MHz external reference. Each signal path achieves a gain of 43 dB, a noise figure of 7.4 dB, and an IIP3 of -11 dBm. The eight-path array achieves an array gain of 61 dB and a peak-to- ratio of 20 dB and improves the signal-to-noise ratio at the output by 9 dB.     

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.