A low-power,wide-range variable gain CMOS RF transmitter for 900 MHz wireless communications

This paper presents a low-power, wide-range variable gain RF transmitter for 900 MHz-band wireless communication applications based on a standard 0.18 μm CMOS technology. A very wide-range variable gain and high linearity up-conversion mixer is obtained by using a newly transconductance stage. High linearity at low power dissipation driver amplifier can be obtained by adopting a folded cascode topology with an additional gate-source capacitor. The measured results show conversion gain of 16 dB, dB-linear gain variation of 47 dB with the linearity error less than ±0.5 dB, output P-1 dB of 2 dBm, and OIP3 of 12 dBm while dissipating 4 mA from 1.25 V supply.     

A 5.2 mW 240–550 MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18 μm CMOS process

A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-μm CMOS technology is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240–550 MHz. The gain of the filter is tuned about 44 dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4 dBm is achieved for a power consumption of 5.2 mW from a 1.8 V power supply. Merging LPF and VGA into one block can efficiently reduce the power consumption and the chip area of the analog baseband channel while achieving a high linearity.     

A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

A 330?MHz 11?bit 26.4?mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is designed and experimental results are presented. The sample-and-hold circuit operates up to 330 MHz of sampling frequency with less than −68.3 dB of total harmonic distortion, corresponding to 11 bits for an input 80.24 MHz sinusoidal amplitude of 1.2V _pp at a 3 V supply. This total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.2 V step input, and 1.2V _pp full-scale differential input range are achieved. The circuit dissipates 26.4 mW with a 3 V power supply.     

A 250 MHz 11 bit 22 mW CMOS low-hold-pedestal fully differential sample-and-hold circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes improved bootstrapped input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 250 MHz of sampling frequency with less than −70 dB of total harmonic distortion corresponding to 11 bits for an input 60.8 MHz sinusoidal amplitude of 1.8 V _pp at a 3 V supply. The total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.8 V step input, and 1.8 V _pp full-scale differential input range are achieved. The circuit dissipates 22 mW with a 3 V power supply.     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

An ultra low power,low voltage tailless QFG based differential amplifier with High CMRR,rail to rail operation and enhanced slew rate

This paper proposes a novel tailless ultra low power low voltage high CMRR differential amplifier (D.A.) with rail-to-rail input common mode range (ICMR) based on quasi floating gate (QFG) transistors. For low voltage operation, the tail current source of the conventional D.A. is removed and the resulted lack of CMRR is highly compensated by means of two simple inverters. The required supply voltage is only VGS + VDS_sat (with their usual meanings of symbols) which is one VDS_sat lower than the required supply voltage for the conventional D.A. Unlike the conventional differential amplifier, slew rate (SR) in the proposed one is not limited by the tail current source and is determined by the amplitude of input signals. The principle of operation, small signal analysis and the formula of the most important parameters of the proposed D.A. are presented. HSPICE simulation results using TSMC 0.18 μm CMOS process parameters and ±0.4 V supply voltage are presented which verify the high performance of the proposed scheme. The simulation results show a rail-to-rail operation and 121 dB CMRR for the proposed tailless differential amplifier. The corner case simulation results are also provided which show a robust performance for the proposed structure. Its unity gain bandwidth product is 72.3 MHz that is 2.31 times larger than that of conventional differential amplifier. Positive and negative SRs are improved by a factor of 7.4 and 3.58 times respectively compared to conventional one. It has also an ultra low power dissipation of 6.89 μW.     

A Low Power Reconfigurable Analog Baseband Block for Software Defined Radio

In this paper, an inverter based transconductor using double CMOS pair is proposed for implementation of a reconfigurable analog baseband block consisting of a variable gain amplifier (VGA) and a second order lowpass G_m-C filter. The centre frequency of the filter is varied using current steering DAC. Major contributions of this paper are: proposal for operating the transconductance (G_m) stage and current steering DAC in sub-threshold region in order to minimize the power dissipation, design of variable gain amplifier (VGA) using switched G_m cells with dummy stages, proposal for a digital tuning technique for the filter based on phase comparison method for compensation against process, voltage and temperature variations. The proposed analog baseband block is designed and implemented on TSMC-0.18 μm CMOS process with 1.8 V supply using g_m/I_d design methodology. The post layout simulation results demonstrate the tunability of the centre frequency from 100 KHz to 20 MHz which meets the requirements of zero IF receivers for SDR applications. The third order input intercept point (IIP3) is found to be 15 dBVp for an input signal of 100 mVp. The power dissipated by the baseband block is 1 mW and 5 mW at 100 KHz and 20 MHz respectively and it requires silicon area of 0.173 mm². The SFDR over the entire bandwidth is 58 dB. The proposed approach guarantees the upper bound on THD to be-40 dB for 300 mVpp signal swing. The use of inverters with double CMOS pair results in 34 dB higher PSRR compared to those using push pull inverter.     

1 V fully balanced differential amplifiers: Implementation and experimental results

We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.     

A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1 MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6 μs, at full load transition. The total ground current including the bandgap reference circuit is 28 μA and the active chip area measures 290 μm × 360 μm in a 0.18 μm CMOS technology.     

A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.     

A 5.4-GHz high-<Emphasis Type="Italic">Q</Emphasis> tunable active-inductor bandpass filter in standard digital CMOS technology

A transistor-only CMOS active-inductor with an all-NMOS signal path is presented. By tuning the varactor-augmented parasitic capacitance at the only internal node the circuit losses from submicron MOSFETs can be partially or fully compensated to permit realizing unlimited values of Q, with little frequency and no power-consumption penalties. Transistor-only second-order bandpass filters using the active inductor were built in the TSMC 0.18-μm CMOS process, and high filter Q was obtained by tuning the varactor. The highest center frequency measured was f ₀ = 5.7 GHz for 0.2-μm gate lengths and the maximum repeatably measured Q was 665. Lower Qs can be obtained by reducing the capacitive compensation or by adjusting the circuit biasing. f ₀ and Q are tunable via separate varactors. IIP ₃ and input 1-dB compression point were simulated as 0.523 V_PP and 0.128 V_PP (−1.65 and −13.9 dBm from a 50-Ω source) at 5.7 GHz with Q = 100 and midband gain equal 4.7 dB. For the same conditions, the output noise and noise figure (R _S = 50 kΩ) were simulated to be 0.8 μV/Hz^1/2 and 25.6 dB, respectively. The filter core occupies an area of 26.6 μm × 30 μm and dissipates 4.4 mW at 5.4 GHz from a 1.8-V power supply. As the circuits use only MOSFETs they are fully compatible with standard digital CMOS processes. f ₀ statistics were obtained by measuring 40 chips at identical biasing condition.     

An inner ESR-fungible compensation technique for ultra low power low dropout regulators

An inner ESR-fungible compensation technique was proposed in this paper to replace the conventional ESR compensation for low dropout regulator (LDO). This technique has been adopted in an ultra low power LDO, the quiescent current of which is only 0.9 μA and the static power consumption is less than 3 μW in typical condition. The proposed LDO can be stable enough with a small 1-μF ceramic capacitor by using this compensation technique, so it is very suitable for portable design due to the low cost and small PCB area. It has been fabricated based on a standard 0.5-μm CMOS technology, and the validity and feasibility of the proposed compensation method has been proved by the measurement results.     

Low-voltage CMOS subthreshold four-quadrant tripler

A CMOS four-quadrant tripler using transistors operated in the subthreshold region is presented. The goal of this circuit is to realize the product of three input signals. This circuit has been implemented in a 0.8 m single-poly double-metal n-well CMOS process. Experimental results show that for a power supply of ±1.5V, the linear input range of this tripler is within ±100mV with the linearity error less than 2%. The total harmonic distortion is less than 2.5% with input range up to ±100mV. The-3dB bandwidth of this tripler is measured to be about 700 kHz.     

Mismatch reduction technique for transistors with minimum channel length

An analog calibration technique is presented to improve the parameter matching between transistors in the differential high-frequency signal path of analog CMOS circuits. It can be applied for mismatch reduction in differential broadband amplifiers and direct down-conversion mixers in which short-channel devices are utilized to minimize bandwidth reduction from parasitic capacitances. In general, the proposed methodology is suitable for radio frequency (RF) applications in which direct matching of the transistors is undesired because sophisticated layout practices would increase the coupling between the high-frequency paths. The approach involves auxiliary devices which sense the existing mismatch as part of a feedback loop for error minimization. This technique is demonstrated with a differential amplifier that has a loaded gain and −3 dB frequency of 12.9 dB and 2.14 GHz, respectively. It was designed in 90 nm CMOS technology with a 1.2 V supply. Monte Carlo simulations indicate that the 4.06 mV standard deviation of the amplifier’s anticipated input-referred offset voltage improves to 0.76–1.28 mV with the mismatch reduction loop, which is contingent on the layout configuration of the calibration circuitry. The associated drain current mismatch reduction for the transistor pair under calibration in the amplifier core is from 3.1% to 0.6–1.0%.     

An ultra-low-power CMOS symmetrical OTA for low-frequency <Emphasis Type="Italic">G</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript>-<Emphasis Type="Italic">C</Emphasis> applications

In this paper an ultra-low-power CMOS symmetrical operational transconductance amplifier (OTA) for low-frequency G _m -C applications in weak inversion is presented. Its common mode input range and its linear input range can be made large using DC shifting and bulk-driven differential pair configuration (without using complex approaches). The symmetrical OTA was successfully verified in a standard CMOS 0.35-μm process. The measurements show an open loop gain of 61 dB and a unit gain frequency of 195 Hz with only 800 mV of power supply voltage and just 40 nW of power consumption. The transconductance is 66 nS, which is suitable for low-frequency G _m -C applications.     

Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-μm 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P_-1 dB)(P_{{-1}\,{\rm dB}}) of −13.5 dBm and the input-referred third-order intercept point (P _IIP3) of −1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 ×0.721.45 \times 0.72 mm² including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.     

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 μm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 μV and the error introduced by the rectification with respect to the non rectified signal is less than −100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.     

Distortion in polar modulated CMOS RF power amplifiers

Polar modulation of a switching RF amplifier is an excellent candidate to combine both linearity, efficiency and CMOS integration for RF power amplifiers used in mobile and wireless communication systems. In this paper, the different sources of distortion associated with polar modulation are discussed and verified by measurement results. A fully integrated linearized CMOS RF Power Amplifier for GSM–EDGE, realized in a 0.18 μm CMOS technology, is used as a benchmark to validate the presented theory. It is demonstrated how the combination of a differential delay between the amplitude signal and the phase signal, together with the AM–PM distortion of the Class E amplifier, generates an asymmetry in the output spectrum. The effect of low-pass filtering of the envelope signal is investigated and the degradation on the linearity with and without delay adjustment is given.     

A new true RMS-to-DC converter using up-down translinear loop in CMOS technology

In this paper a new true current-mode RMS-to-DC converter circuit based on a square-root-domain squarer/divider and simplified current-mode low pass filter is presented. The circuit is designed by employing up-down translinear loop and using of MOSFET transistors that operate in strong inversion saturation region. The converter offer advantages of two-quadrant input current, low circuit complexity, large dynamic range, low supply voltage (1.2 V) and immunity from the body effect. Moreover, the power consumption of the circuit for the maximum accepted input current is less than 100 μW and does not need extra biasing to inject current into transistors. The circuit has been simulated by HSPICE. The simulation results with 0.18 μm CMOS technology are seen to conform to the theoretical analysis and shows benefits of the proposed circuit. Simulation results show high performance of the proposed circuit.