Charge-coupled devices with submicron gaps

The fabrication of two-phase buried channel charge-coupled devices with 100 transfer electrodes is described. The gate electrodes were constructed using only one level of polysilicon and with interelectrode gaps of approximately 0.5 µm. The edge etch technique was employed to provide 750 Å wide windows to the polysilicon layer and then etching the polysilicon structure through these windows to produce submicron gaps. The use of the device as an analog delay line was demonstrated with a typical transfer efficiency of 0.99992 at 5 MHz.     

Composite silicide gate electrodes—Interconnections for VLSI device technologies

A potentially severe limit on density, performance, and wirability of polysilicon-gate technologies for VLSI applications, is the high resistivity of polycrystalline silicon. Composite structures of highly conductive molybdenum or tungsten disilicide on top of polysilicon (polycide) are shown to be a viable alternative gate electrode and interconnect level. Sheet resistance values of 1-3 Ω/□ for an integrated structure are easily attainable. IGFET devices fabricated to channel lengths of ≥ 1.4 µm show the polycide devices to be indistinguishable from normal polysilicon gate devices.     

High-speed, low-power, implanted-buried-oxide CMOS circuits

CMOS ring oscillators with channels less than 1/2 µm long were fabricated in implanted-buried-oxide, silicon-on-insulator films using direct-write electron-beam lithography. Transistors with polysilicon gate lengths as short as 0.4 µm and effective channel lengths as short as 0.21 µm operate satisfactorily. Ring oscillators have delays per gate of 52 and 83 ps and power-delay products of 55 and 5 femtojoules for supply voltages of 5 and 3.3 V, respectively.     

Annealing of oxide fixed charges in scaled polysilicon gate MOS structures

Annealing of oxide fixed charges (QF) under polysilicon gate in scaled MOS structures was studied. Our results indicate that, even for a gate width as small as 1.25 µm, QFunderneath the polysilicon gate is unaffected by further processing steps, including high-temperature oxidizing ambients. In other words, the QFtriangle reduces to a horizontal line, even for scaled down polysilicon gate MOS devices. This result has important practical implications, because poly-Si gate is the dominating MOS technology today. A two-dimensional oxygen diffusion model is proposed to explain this phenomenon. Numerical solution was carried out based on the finite difference method. It will be shown that the polysilicon gate not only acts as a barrier to oxygen above the gate oxide, it also keeps oxygen away from the SiO_{2}- Si-substrate interface under the gate edges, thus very effectively shielding the gate oxide from the ambient.     

High-speed polysilicon emitter—base bipolar transistor

High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at VCE= 3 V, LVCEO= 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 µm, and a 1.3-µm-thick arsenic-doped LPCVD epitaxial layer of 0.25 Ω.cm is utilized. Emitter-base (E-B) junctions formed by direct implantations of arsenic and boron ions into a substrate were compared with junctions induced by diffusing dopants from implanted polysilicon. In the case of diffused junctions, an emitter junction depth of less than 500 Å along with a 1000-Å base width can be obtained.     

An advanced PSA technology for high-speed bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double polysilicon electrodes, the emitter area is reduced to 1 µm × 3 µm and the base junction is reduced to 0.3 µm. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.     

0.4-µm gate-length devices fabricated by contrast-enhanced lithography

This letter describes the fabrication of submicrometer polysilicon-gate MOS devices by an advanced optical process called contrast enhancement. Functional devices having gate lengths as small as 0.4 µm were fabricated with this process. Contrast-enhanced lithography (CEL) allows usable photoresist patterns to be fabricated at smaller dimensions than is possible with conventional resist. The simultaneous replication of mask dimensions for isolated lines at 0.35 µm and above was achieved in this work using a single exposure on an Optimetrix 10:1 DSW system. Contrast enhancement has been applied to the fabrication of n-channel MOS devices having gate lengths from 0.4 to 1.5 µm in steps of 0.1 µm. Long-channel devices were also fabricated. The transconductance of the 0.4-µm devices is 40 mS/mm at Vds= 5 V. Threshold voltages (Vds= 0) are nearly independent of gate length, ranging from 1.21 to 1.31 V over the 7.5- to 0.4-µm range in gate length. The effective mobility for long-channel devices is 430 cm²/V.s.     

A fine emitter transistor fabricated by electron-beam lithography for high-speed bipolar LSI's

A highly stable, high-performance bipolar transistor with a 1/4-µm emitter is developed. This is accomplished by using advanced electron-beam (EB) lithography and polysilicon reactive ion etching (RIE). Results show that the minimum emitter width is only 0.2 µm and the emitter width accuracy is ±0.06 µm. In addition, the gate delay is reduced from 190 to 100 ps/gate for 25-stage, three-input ECL circuits. The effects of an ultra-narrow emitter on transistor characteristics are also studied.     

Fabrication of submicrometer MOSFET's using gas immersion laser doping (GILD)

The fabrication of MOSFET's with submicrometer gate lengths using Gas Immersion Laser Doping (GILD) to dope the source-drain and gate regions of n-channel devices is described. The GILD step relies on a melt/regrowth process, initiated by a pulsed excimer laser (XeCl, λ = 308 nm), to drive in a dopant species adsorbed on the clean silicon surface. High dopant concentrations (1 × 10¹⁹to 2 × 10²¹cm^-3) and shallow junctions (600-1000 Å) make this process ideally suited for source-drain formation in submicrometer structures. In this work the transistors are fabricated using an otherwise conventional NMOS process. The resultant devices have similar source-drain Rsheetvalues and lower poly Rsheetwhen compared to devices fabricated using a conventional implanted source-drain and diffused polysilicon gate. Short-channel devices (L_{poly} = 0.9µm) exhibit excellent I-V characteristics and little change in Vt.     

Very short gate-length GaAs MESFET's

GaAs MESFET's with gate lengths ranging from 0.36 µm down to 0.055 µm, the smallest so far reported, have been fabricated using electron-beam lithography. DC output characteristics were obtained from all of the devices tested and transconductances up to 300 mS/mm were measured. However it was observed that there is a maximum drain-source voltage that can be pinched off in these short gate devices. This voltage varies exponentially from 1 V in the 0.055-µm gate devices to 6 V in the 0.36-µm device. It is speculated that this effect is due to current injection into the buffer layer.     

Buried channel MOSFET's with gate lengths from 2.5 µm to 700 Å

High resolution electron beam lithography has been used to fabricate ion implanted buried channel MOSFET's with gate lengths ranging from 0.4 µm to 700 Å. Similar devices were also fabricated on the same chip using optical lithography with gate lengths of 2.5 µm. These devices include some with the smallest lithographically defined gates ever made in silicon; similar devices should help define the limits to miniaturization in semiconducting devices.     

Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p⁺substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p⁺substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p⁺substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.     

A new edge-defined approach for submicrometer MOSFET fabrication

A novel technique employing vertical (anisotropic) dry etching for fabricating edge-defined submicrometer MOSFETs is described, and preliminary results are presented. Three basic process techniques are employed: formation of an edge-defined submicrometer element, pattern transfer of the element into an underlying doped polysilicon gate layer, and passivation of the FET using a sidewall oxide. The submicrometer element formation technique is limited to linewidths in the 0.1 µm to 0.4 µm range. Characterization of MOSFETs, having physical channel lengths ∼0.1 µm to 0.15 µm and believed to be the world's smallest MOSFET's reported to date, is discussed.     

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-Å n⁺poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm²/V.s. The drain-to-source breakdown voltage exceeds -20 V.     

1-µm MOS process using anisotropic dry etching

Anisotropic and selective etching of silicon has been obtained using a planar-reactive sputter-etching system and CCl3F gas. The Si to SiO2etch-rate ratio was 5 : 1. This etch process in CCl3F was interpreted as mainly involving physical reaction as opposed to etching in SF6. The influence of reactive sputter etching on junction leakage and threshold voltage shift, in comparison with a conventional wetetch process, could not be observed in the electrical characteristics of polysilicon gate MOS devices. An all dry-etched MOS process, consisting of an anisotropic etching for Si3N4, polysilicon, SiO2, and aluminum, was applied to the fabrication of a 1-kbit static RAM with 1-µm minimum geometry. It was confirmed that this anisotropic etching technology was useful for very fine-geometry patterning and could be applied to a 1-µm MOSLSI manufacturing process.     

A new VLSI memory cell using DMOS technology (DMOS cell)

A high-density dynamic memory cell using DMOS technology (DMOS cell) is proposed. A DMOS cell consists of an n-channel DMOSFET as a read gate and a p-channel MOSFET as a write gate with extensive node sharing. Since n-DMOSFET threshold state is nondestructively detected, the readout signal voltage is almost invariant to scaling. The cell area, which is made small by using two polysilicon layers and self-aligned structure, is about 50 percent of the conventional one-transistor memory cell area. An analytic model for DMOS cell readout voltage is proposed. From this model, the optimum DMOS cell structure, which gives more than 0.7-V readout voltage with 2-µm channel length, is found for 5-V power supply operation. Experimental data support this model. A 7-µA readout current per 1-µm channel width is obtained for 400-Å gate oxide test cell. The complete memory operation is confirmed with a 2 × 2 test cell array.     

The formation of shallow low-resistance source—Drain regions for VLSI CMOS technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p⁺regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n⁺and p⁺junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Composite TiSi2/n + poly-Si low-resistivity gate electrode and interconnect for VLSI device technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi2polycide gate. A coevaporated TiSi2polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2because of lower oxygen contamination. The coevaporation technique to form TiSi2polycide with a sheet resistivity of 1 Ω/square (bulk resistivity of 21 µΩ.cm) is described. Anisotropic etching of nominally 1-µm lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi2polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

Analysis of the properties of three-terminal transferred-electron logic devices

A two-dimensional analysis of Schottky-barrier gate GaAs logic devices utilizing the transferred-electron effect is described. The analysis is used to study the basic properties of two devices with anode to cathode spacing of 13 µm and 33 µm. The reduction in current drop due to the presence of the gate is discussed. The switching properties of the 13-µm device are studied for operation with either anode or cathode resistance. A gate delay of 30 ps and a total gate power of 180 mW is estimated.