Consideration of discrete interface traps in InGaAs/GaAs heterojunctions

Poisson's equation has been applied to model the capacitance-voltage (C-V) profile of a Schottky-barrier n-N heterojunction of Au/nIn0.1Ga0.9As/NGaAs. Interface traps, represented either as a box or sheet of charge, have been included in the calculation. Two electron accumulation peaks are observed. One, next to the region depleted of electrons, is related to the interface trap occupancy, and the other is related to the two-dimensional electron gas at the heterojunction. Qualitative agreement is obtained between the calculated and experimentally determined C-V electron profile (300 to 77 K) if a trap EC- 0.13 eV at a concentration -8 × 10¹⁰cm^-2in a 300-Å boxlike distribution is included in the calculation. For MBE grown nIn0.1Ga0.9As/NGaAs deep-level transient spectroscopy suggests that the interface traps are at EC- 0.13 and 0.17 eV with capture cross sections of about 2 × 10^-14and 1 × 10^-15is cm².     

Anodic oxidation of Si in oxygen/chlorine plasma

By adding a few percent of chlorine to oxygen plasma, the anodization rate of Si was enhanced; for example, the rate was doubled for oxygen containing 3-percent chlorine. With a chlorine concentration of 1.5 percent, the density of trap states at the Si-SiO2interface was reduced from 7×10¹¹/cm².eV to 5×10¹¹/cm².eV at the midgap of Si; after annealing at 800°C in argon for 60 min, it was reduced to 8 × 10¹⁰/cm².eV, and did not return to the original value after heating the specimen to 800°C. The density and capture cross section of traps in plasma-anodic oxide were also measured using the constant-current avalanche-injection method. The number of electron traps with small cross sections in plasmaanodic SiO2films was reduced by annealing them at 800°C in argon, but SiO2films which were anodized in oxygen/chlorine plasma showed an increase of trap density under the same annealing condition.     

P-type 4H and 6H-SiC high-voltage Schottky barrier diodes

High-voltage Schottky barrier diodes have been successfully fabricated for the first time on p-type 4H- and 6H-SiC using Ti as the barrier metal. Good rectification was confirmed at temperatures as high as 250°C. The barrier heights were estimated to be 1.8-2.0 eV for 6H-SiC and 1.1-1.5 eV for 4H-SiC at room temperature using both I-V and C-V measurements. The specific on resistance (R_on,sp) for 4H- and 6H-SiC were found to be 25 mΩ cm^-2 and 70 mΩ cm^-2 at room temperature. A monotonic decrease in resistance occurs with increasing temperature for both polytypes due to increased ionization of dopants. An analytical model is presented to explain the decrease of R_on,sp with temperature for both 4H and 6H-SiC which fits the experimental data. Critical electric field strength for breakdown was extracted for the first time in both p-type 4H and 6H-SiC using the breakdown voltage and was found to be 2.9×10⁶ V/cm and 3.3×10⁶ V/cm, respectively. The breakdown voltage remained fairly constant with temperature for 4H-SiC while it was found to decrease with temperature for 6H-SiC     

Electronic properties of the silicon-thermally grown tantalum oxide interface

MOS capacitance measurements showed that the Si-Ta2O5interface prepared by thermal oxidation at ∼530°C of vacuum deposited Ta film followed by a heat treatment at 350°C in N2-H2is characterized by a negative "oxide" charge (6 × 10¹¹e/cm^-2at flat-band) and by an interface state density of ∼ 1 × 10¹²cm^-2(eV)^-1. The room temperature instability is small. The breakdown strength is >8 × 10⁶V/cm.     

Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor

We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO₂ interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10¹² cm^–2 and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.     

Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

Dielectric loss and current—Voltage measurements in sodium-contaminated Si—SiO2—Cr structures

A detailed study of the small-signal ac response of ntentionally sodium-contaminated Si-SiO2-Cr structures has been made with mobile ion concentrations of 10¹⁰-10¹²ions/cm², in the frequency range of 0.05-100 Hz, between temperatures of 300 and 450°C. The time dependence of the observed relaxation phenomena, attributed to the existence of deep traps near the SiO2-Cr interface, is slow enough to consider the measured relaxation spectra as quasi static. The dc bias dependence of the relaxation mechanism, manifested by a loss maximum around 0.6 V and by a monotonic decrease of the absorption frequency with increasing bias, is ascribed to shallow traps located at the SiO2-Cr interface. The trapping as well as the long range migration of Na⁺ions in SiO2has been carefully studied by I-V and C-V measurements carried out on both contaminated and on ultraclean samples. The long-range motion of the ions leads to the thickness dependence of the relaxation time. However, since the ac response is determined in the two halves of the measuring cycle alternately by the migration of ions in the bulk of the SiO2and by their emission from the shallow traps, the relaxation time is also dependent on the effect of the traps. Consequently, the observed bias-dependent activation energies, ranging from 0.91 to 1.21 eV, may also be interpreted as intermediate values, arising from the conduction of Na⁺ions in SiO2films with an activation energy of less than 0.91 eV, and from the release of ions from the traps having activation energies equal to or greater than 1.21 eV.     

An EEPROM cell using a low barrier height tunnel oxide

A new simple method to fabricate a thin oxide with low barrier height is proposed. An oxide is grown on a heavily implanted silicon substrate with As or P in excess of 5 × 10¹⁴/cm². When the oxide was grown in H2O + Ar gas after Ar annealing, the barrier height of the oxide conduction band with respect to the silicon conduction band decreased to 1.8 eV, about one half of the ordinary value of 3.2 eV. This phenomenon was applied to an EEPROM cell, which showed superior WRITE/ERASE characteristics. A moderately implanted As (2.5 × 10¹⁵/ cm²) sample shows excellent WRITE/ERASE endurance, over 10⁶cycles with 2-V Vthwindow, which could not realized by using an ordinary oxide.     

The transport and isolation properties of polycrystalline GaAs selectively grown by molecular beam epitaxy

Selective-area polycrystalline GaAs using SiO2masking is planarly grown by molecular beam epitaxy (MBE). The electric properties of the polycrystalline GaAs are investigated because this technology is very promising for device isolation in GaAs integrated circuit and electro-optic integration. Compared with the isolation characteristics of semi-insulating GaAs, polycrystalline GaAs has similar low-field resistivity, higher high-field leakage current, and no well-defined trap-fill-limited voltage. The grain boundary (GB) states of polycrystalline GaAs trap negative charge that builds up a potential barrier to hinder electron current. The GB density of states profile estimated from the IV characteristics shows a peak value 5 × 10¹²cm^-2.eV¹and a wide energy distribution, 0.33 eV above the equilibrium Fermi energy.     

A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization

A study is made of noise in p- and n-channel transistors incorporating SiGe surface and buried channels, over the frequency range f=1 Hz–100 kHz. The gate oxide is grown by low temperature plasma oxidation. Surface n-channel devices are found to exhibit two noise components namely 1/f and generation–recombination (GR) noise. It is shown that the 1/f noise component is due to fluctuations of charge in slow oxide traps whilst bulk centers located in a thin layer of the semiconductor close to the channel, give rise to the GR noise component. The analysis of the noise data gives values for the density D_ot of the oxide traps in the SiGe and Si nMOSFETs of the order 1.8×10¹² and 2.5×10¹⁰ cm⁻² (eV)⁻¹, respectively. The density D_GR of the bulk GR centres is equal to 3×10¹⁰ cm⁻² in both the SiGe and Si devices. The electron and hole capture cross-sections for these centres as well as their energy level and their depth below the oxide/semiconductor interface are also the same in the devices of both types. This suggests that those GR centers are of the same nature in all devices studied. p-Channel devices show different behaviour with only a 1/f noise component apparent in the data over the same frequency range. Buried SiGe channel and Si control devices exhibit quite low and similar slow state densities of the order low to mid 10¹⁰ cm⁻² (eV)⁻¹ whereas surface p-channel devices show even higher slow state densities than n-channel counterparts. The Hooge noise characterized by the Hooge coefficient _H=2×10⁻⁵ is also detected in some buried p-channel SiGe devices.     

Properties of ion-implanted junctions in mercury—cadmium—telluride

The formation of n-p junctions by ion-implantation in Hg0.71Cd0.29Te is shown to be a result of implantation damage. n-p photodiodes have been made by implantation of Ar, B, Al, and P in a p-type substrate with acceptor concentration of 4 × 10¹⁶cm^-3. The implanted n-type layer is characterized by sheet electron concentration of 10¹⁴to 10¹⁵cm^-2and electron mobility higher than 10³cm². V^-1. s^-1, for ion doses in the range 10¹³-5 × 10¹⁴cm^-2. The photodiodes have a spectral cutoff of 5.2 µm, quantum efficiency higher than 80 percent, and differential resistance by area product above 2000 Ω . cm²at 77 K. The temperature dependence of the differential resistance is discussed. The junction capacitance dependence on reverse voltage fits a linearly graded junction model. Reverse current characteristics at 77 K have been investigated using gate-controlled diodes. The results suggest that reverse breakdown is dominated by interband tunneling in field-induced junctions at the surface, for both polarities of surface potential.     

Erase/write cycle tests of n-MOSFETs with Si-implantedgate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V     

The influence of bulk traps on the charge-transfer inefficiency of bulk charge-coupled devices

One of the possible causes of a finite charge-transfer inefficiency in bulk charge-coupled devices (BCCD's) is the presence of bulk traps in the n-type silicon layer through which the charge packets are transferred. To determine the relative importance of the contribution of traps, we measured charge transfer inefficiency as a function of temperature. In most of the devices investigated, this measurement results in two broad peaks due to the presence of traps at 0.25 and 0.54 eV below the conduction band edge. The concentration of these traps varied from batch to batch between values of 5 × 10¹⁰cm^-3and 1 × 10¹²cm^-3.     

Characteristics of pulse excited electroluminescence from ZnS films containing rare earth fluroide

The transient behavior of the electrical and the optical properties under pulse excitation has been studied and analyzed in detail on the electroluminescent devices made of Au-ZnS: NdF3- Ta2O5-Ta composite films. The ZnS-Ta2O5interface is capable of accommodating a large number of trapped electrons, up to 10¹³cm^-2, with the majority of the interfacial states located at a fixed energy below the conduction band of ZnS. Carrier injection is achieved by electrons tunneling through the Au-ZnS Schottky barrier at a field of 2.6×10⁶V/cm. The threshold field of impact excitation for 1 percent NdF3in ZnS was found to be 1.5×10⁶V/cm; while the coefficient of impact excitation at 2.6×10⁶V/cm was estimated to be 1750 cm^-1. In addition, the emission time constants of several rare earth fluorides were also studied.     

GaAs-MOS capacitor with native oxide film anodized in nonaqueous electrolyte

Anodic oxidation of GaAs in a new nonaqueous electrolyte and MOS characteristics are described. The anodic oxide film with specific resistivity of $\text{10}{}^{14}\text{–10}{}^{15}\text{Ω}\text{cm}$ and breakdown field strength of 2 × 10⁶ V/cm was grown at a rate of 22 Å/V for a current density of 0.5 mA/cm² in the electrolyte of a saturated ethylene glycol solution of potassium dichromate. A linear relationship between the oxide thickness and the forming voltage was maintained in spite of nonlinearity between the forming voltage and the anodization time. After a shorter time annealing for about 30 min than in an aqueous electrolyte, the new MOS capacitor shows improved interface properties with a small hysteresis and has a noticeable feature of sensitivity to light, and no hysteresis in the C-V curve was observed under light illumination of higher photon energy than about 1 eV.     

Modeling the variation of the low-frequency noise in polysiliconemitter bipolar junction transistors

The variation of the low-frequency noise in polysilicon emitter bipolar junction transistors (BJTs) was investigated as a function of emitter area (A_E). For individual BJTs with submicron-sized A _E, the low-frequency noise strongly deviated from a 1/f-dependence. The averaged noise varied as 1/f, with a magnitude proportional to A_E^-1, while the variation in the noise level was found to vary as A_E^-1.5. A new expression that takes into account this deviation is proposed for SPICE modeling of the low-frequency noise. The traps responsible for the noise were located at the thin SiO₂ interface between the polysilicon and monosilicon emitter. The traps' energy level, areal concentration and capture cross-section were estimated to 0.31 eV, 6×10⁸ cm^-2 and 2×10^-19 cm ², respectively     

Ge3N4-InP MIS structures

MIS structures were fabricated by the low temperature pyrolytic deposition of Ge3N4on n-InP. The interface characteristics of the devices were found to depend on Ge3N4deposition parameters. For optimum deposition conditions, C-V and G-V measurements suggest the presence of an average interface state density of (2-4-) × 10¹¹cm^-2ev^-1with a time constant of 8 µs. No major hysteresis was observed in the C-V plot and the data indicates some inversion charge build-up under the application of large negative bias which could be useful for the fabrication of inversion mode MISFET's.     

Relating computer simulation studies with interface state measurements on MIS solar cells

A lock-in-amplifier technique has been used to measure interface state density (NSS) values ranging from 2 × 10¹¹-3 × 10¹³states/cm². eV depending on energy in the gap, type of Si substrate, and choice of Schottky metal used in MIS diodes. Polycrystalline, ribbon, and     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.     

Ion-dosage-dependent room-temperature hysteresis in MOS structureswith thin oxides

Two sets of metal-oxide-silicon (MOS) structures with oxide thicknesses of 115 and 350 Å, respectively, were exposed to 16-keV Si ion beams after dry oxidation. Small-signal capacitance-voltage measurements at room temperature revealed a hysteresis effect in the ion exposed samples, whose magnitude and direction depended on the ion dosage. No hysteresis could be detected in the control (unimplanted) samples. Mobile charge species in the oxide dominated the hysteresis effect for dosages below 10¹³/cm². Around this dosage, electron trapping/detrapping at the Si-SiO₂ interface began to take place. From the rate of the parallel voltage shifts of the C-V characteristics with respect to time, electron trapping and the mobile oxide charge transfer from the silicon/oxide to the aluminum/oxide interface were found to be faster than electron detrapping and the mobile oxide charge transfer form the oxide/Al to the Si-SiO₂ interface. With increasing dosage, the magnitude of the hysteresis came down and reversed its sign as the dosage approached 10¹³/cm². Experimental results suggest immobilization of the mobile oxide charge by lattice disorder induced by the energetic ions, and generation of oxide electron traps in the vicinity of the silicon/oxide interface after the lattice damage becomes heavy