Feedback supported isolation structure for blocking of minority leakage carriers in power integrated circuits

A combination of two conventional junction isolation structures is used to produce a device, which significantly improves the blocking of minority carriers injected into the substrate of a power IC due to switching of an inductive load. Simulation results show that the connection scheme employed greatly enhances the efficiency of the structures. A substrate current reduction of up to four orders of magnitude compared to conventional junction isolation structures is achieved. The significance of doping profiles in the p-sinker region is evaluated.     

Effects of Zn Doped Mesa Sidewall on Gain Enhanced InGaAs/InP Heterobipolar Phototransistor

The excellent detectability of the gain enhanced InGaAs/InP heterobipolar phototransistor (GE-HPT) is demonstrated and attributed to a reduction in the reverse leakage current at the base-collector junction and the enhancement of current gain at the emitter-base junction achieved by using a current blocking structure with a Zn doped mesa sidewall. The common emitter grounded current gain agrees well with the photo-conversion efficiency of several tens of thousands of A/W at incident optical powers in the hundred nanowatt to sub-picowatt range over several orders of magnitude. The deep mesa structure in the GE-HPT is also effective in ensuring superior isolation of better than 25 dB between adjacent arrays.      

An Experimental Study on High-Frequency Substrate Noise Isolation in BiCMOS Technology

In this letter, four substrate noise isolation structures in standard 0.18-mum SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P⁺ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which |S₂₁| was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.     

MOS control device concepts for AC-AC matrix converter applications: the HCD concept for high-efficiency anode-gated devices

Reverse blocking MOS controlled devices will enable high efficiency ac-ac matrix converter systems to replace dc-linked type circuits. The trend in bidirectional switches is to replace the combination of a unidirectional blocking device and a diode with a monolithic reverse blocking device only. The diode on-state loss is eliminated, part count is reduced, and the system is less bulky. This paper discusses the various reverse blocking concepts suitable for MOS controlled devices for high voltage matrix converter applications. They include the junction isolation, the trench isolation, and the anode-gated (AG) concepts. AG is the only concept not technologically limited beyond 1200 V. However, increasing drift region thickness with voltage rating necessitates innovations to achieve fast switching and low losses without compromising V/sub ce(sat)/. Herein we propose the high channel density concept to further improve the efficiency of AG devices. Simulation results indicate the concept drastically reduces turnoff losses and improve switching speed.     

Optimization and surface charge sensitivity of high-voltageblocking structures with shallow junctions

The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges. These high-voltage termination structures specifically designed for 1000-V blocking capability lose 25 to 50% of their voltage-blocking capability under 5×10¹¹ cm^-2 net interface state density. In contrast, optimized multiple-zone JTE (MZ-JTE), and offset multiple field plated and field-limiting ring (OFP-FLR) structures will lose only 5% of their respective voltage blocking capabilities under the same surface-charge condition. These improved high-voltage blocking structures do not require additional passivation and process complexities     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

Characterization of spiral inductors with patterned floating structures

The impact of two different types of floating patterns on spiral inductors was investigated. Both patterned trench isolation with a floating p/n junction and floating metal poles were implemented underneath reference spiral inductors. All three types of inductors have an identical spiral geometry. Combination of patterned trench isolation with a floating p/n junction increases maximum quality factor (Q/sub max/) by 17% compared to the reference inductors. The floating metal poles enable adjustment of the frequency at Q/sub max/ (f/sub max/) without hampering the Q/sub max/. A ladder-type lump-element model was employed to analyze inductor performance after it was demonstrated to precisely capture behavior of all three inductors. Enhancement of the quality factor due to patterned trench isolation with a floating p/n junction was found to result from an increment of effective resistivity in substrates. Reduction of the frequency f/sub max/ due to the floating metal poles was caused by increasing effective coupling capacitance between the spiral inductors and substrate.     

Electrical performance and physics of isolation region structures for VLSI

A two-dimensional effect in isolation structures is described. It is shown with computer simulations, mathematical analysis, and experimental measurements that the use of trench-like isolation structures significantly improves device electrical isolation, provided junction depths are less than the trench depth. A potential barrier exists at the corners of the isolation region that dominates the parasitic device's I - V characteristics. A mathematical relation for the subthreshold slope as a function of the interface radius is derived which predicts the slope is flatter and the threshold voltage is increased compared to conventional LOCOS structures. This significantly improves the isolation. The position of the potential barrier is shown to allow scaling of the isolation region width without degrading the isolation. Experimental results have verified the predictions of extensive computer simulations.     

Differentiation of source/drain breakdown mechanisms by a singlering transistor measurment

A measurement technique using a single device to differentiate the effects of junction curvature, surface fields, and isolation implants in MOS source/drain breakdown is described. This use of a single device may complement existing measurement techniques, or be useful for design of test structures in the streets (scribe channels), where the number of devices is pad limited     

Design of a Coaxial Hybrid Junction

The design of a coaxial hybrid junction is discussed. The hybrid consists of a shunt junction and a series junction. The shunt junction is a broad-band stub compensated tee, and the series junction is basically a balun of the type used to excite a slotted dipole. There is inherent isolation between the shunt and series terminals. The useful bandwidth of the hybrid is at least 10 per cent, while the bandwidth of the shunt junction alone exceeds this by a factor of four. Design data are presented for frequency bands centered at 425 Mc and 220 Mc. Many of these hybrids have been manufactured for application, and the performance repeats very well. Performance data are given for VSWR, isolation, and peak power capacity.     

Spectral response of blue-sensitive Si photodetectors in SOI

In this paper, we present a novel blue-sensitive Si photodetector. The detector is realized as a Si diode with a vertical PN junction in the silicon-on-insulator (SOI) thin film for normal incident light. Due to the thin SOI device layer, the photodetector shows a blue-shift spectral response with the peak external quantum efficiency (QE) of 69.6% at wavelength of 480 nm. The photodetector adopts a thin layer of SiO₂ as an antireflection coating and as a blocking layer for shallow ion implantation doping. The isolation trench etched through the SOI thin film to the buried oxide (BOX) provides fully electrical isolation. The device structure is simple and its performance is very high, therefore, it is in favor of monolithically integration with other micro/nanodevices.     

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

According to the avalanche ionization theory,a computer-based analysis is performed to analyze the structural parameters of single-and multiple-zone junction termination extension (JTE) structures for 4H-SiC bipolar junction transistors (BJTs) with mesa structure.The calculation results show that a single-zone JTE can yield high breakdown voltages if the activated JTE dose and the implantation width are controlled precisely and a multiple-zone JTE method can decrease the peak surface field while still maintaining a high blocking capability.The influences of the positive and negative surface or interface states on the blocking capability are also shown.These conclusions have a realistic meaning in optimizing the design of a mesa power device.     

台面结终端高压4H-SiC BJTs的击穿特性研究

根据雪崩碰撞理论,本文对具有台面结构的4H-SiC BJTs中所使用的单区和多区结终端结构参数对击穿电压的影响进行了分析和计算。计算结果表明,在单区结终端结构中,通过精确控制有源JTE的掺杂浓度和离子注入深度可以有效提高台面BJTs器件的击穿电压,而多区结终端结构可以在保持击穿电压不变的前提下降低峰值表面电场。同时文中还对正负表面态或界面态对击穿电压的影响做了详细的计算分析。这些结果对于优化台面功率器件的高压特性有着重要的现实意义。     

0.5μm高速BiCMOS的工艺研究

报道了一套先进的0.5μm高速双层多晶硅自对准BiCMOS制作工艺.工艺中采用了先进的深槽隔离技术、选择性集电极注入(SIC)技术、使用自对准Si3N4/SiO2复合侧墙作为E-B结的隔离、用低能氟化硼取代硼注入基区形成超薄内基区.通过优化BiCMOS制作工艺,最终制作出了性能优良的高速BiCMOS器件.     

A novel dual-polarity device with symmetrical/asymmetrical S-type I-V characteristics for ESD protection design

A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymmetrical I-V characteristics for ESD (electrostatic discharge) applications is presented. The device allows for the dual-polarity conduction with the proper selection of blocking junction configurations. This design enables high-level ESD protections for various mixed-signal integrated circuits operating under a wide range of symmetrical and asymmetrical bias conditions.     

Fabrication of SiC lateral super junction diodes with multiple stacking p- and n-layers

Using epitaxial multiple p-n junction structures of 4H-SiC, lateral super junction diodes were fabricated for the first time. The breakdown voltage of the device was 400 V, which is more than 3/spl times/ higher than the theoretical value calculated for a device with uniformly-doped drift layer (130 V), indicating the effective operation of the super junction structure.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n+-InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n+-InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n+-InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

A new DC Drain-Current-Conductance method (DCCM) for thecharacterization of effective mobility (μeff) and seriesresistances (Rs, Rd) of fresh and hot-carrierstressed graded junction MOSFETs

A simple new DC technique is developed to extract the gate bias dependent effective channel mobility (u_eff) and series resistances (R_s and R_d) of graded junction n- and p-channel MOSFETs. This technique is found to be accurate and effective for devices with differing channel lengths and also for devices after nonuniform hot-carrier degradation. The parameter values extracted provide further insight into the damage mechanisms of hot-carrier stressed graded junction nMOSFETs and are usable in circuit and reliability simulation. This technique is especially useful for the optimization of hot-carrier resistant structures of submicrometer MOSFETs